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[/] [or1k/] [tags/] [rel_29/] [or1200/] [rtl/] [verilog/] [or1200_spram_1024x32.v] - Diff between revs 1200 and 1267
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| Rev 1200 |
Rev 1267 |
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Line 61... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.5 2003/08/19 16:41:23 simons
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// Revision 1.3.4.2 2003/12/09 11:46:48 simons
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// Scan signals mess fixed.
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// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
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//
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//
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// Revision 1.4 2003/08/11 13:32:19 simons
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// Revision 1.3.4.1 2003/07/08 15:36:37 lampret
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// BIST interface added for Artisan memory instances.
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// Added embedded memory QMEM.
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//
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//
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// Revision 1.3 2003/04/07 01:19:07 lampret
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// Revision 1.3 2003/04/07 01:19:07 lampret
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// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.
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// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.
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//
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//
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// Revision 1.2 2002/10/17 20:04:40 lampret
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// Revision 1.2 2002/10/17 20:04:40 lampret
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Line 121... |
`ifdef OR1200_BIST
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`ifdef OR1200_BIST
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//
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//
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// RAM BIST
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// RAM BIST
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//
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//
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input mbist_si_i;
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input mbist_si_i;
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input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
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input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
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output mbist_so_o;
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output mbist_so_o;
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`endif
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`endif
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//
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//
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// Generic synchronous single-port RAM interface
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// Generic synchronous single-port RAM interface
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