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[/] [or1k/] [tags/] [rel_29/] [or1200/] [rtl/] [verilog/] [or1200_spram_64x24.v] - Diff between revs 1179 and 1184
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Rev 1179 |
Rev 1184 |
Line 61... |
Line 61... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.4 2003/08/11 13:32:19 simons
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// BIST interface added for Artisan memory instances.
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//
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// Revision 1.3 2003/04/07 01:19:07 lampret
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// Revision 1.3 2003/04/07 01:19:07 lampret
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// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.
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// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.
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//
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//
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// Revision 1.2 2002/10/17 20:04:41 lampret
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// Revision 1.2 2002/10/17 20:04:41 lampret
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// Added BIST scan. Special VS RAMs need to be used to implement BIST.
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// Added BIST scan. Special VS RAMs need to be used to implement BIST.
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//
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//
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// Internal wires and registers
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// Internal wires and registers
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//
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//
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wire [7:0] unconnected;
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wire [7:0] unconnected;
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`ifdef OR1200_ARTISAN_SSP
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`else
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`ifdef OR1200_VIRTUALSILICON_SSP
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`else
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`ifdef OR1200_BIST
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`ifdef OR1200_BIST
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assign scanb_so = scanb_si;
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assign scanb_so = scanb_si;
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`endif
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`endif
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`endif
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`endif
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`ifdef OR1200_ARTISAN_SSP
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`ifdef OR1200_ARTISAN_SSP
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//
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//
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// Instantiation of ASIC memory:
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// Instantiation of ASIC memory:
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