URL https://opencores.org/ocsvn/or1k/or1k/trunk

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[/] [or1k/] [tags/] [rel_29/] [or1200/] [rtl/] [verilog/] [or1200_top.v] - Diff between revs 1104 and 1200

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Rev 1104	Rev 1200
Line 42...	Line 42...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.10 2002/12/08 08:57:56 lampret`
	`// Added optional support for WB B3 specification (xwb_cti_o, xwb_bte_o). Made xwb_cab_o optional.`
	`//`
`// Revision 1.9 2002/10/17 20:04:41 lampret`	`// Revision 1.9 2002/10/17 20:04:41 lampret`
`// Added BIST scan. Special VS RAMs need to be used to implement BIST.`	`// Added BIST scan. Special VS RAMs need to be used to implement BIST.`
`//`	`//`
`// Revision 1.8 2002/08/18 19:54:22 lampret`	`// Revision 1.8 2002/08/18 19:54:22 lampret`
`// Added store buffer.`	`// Added store buffer.`
Line 135...	Line 138...
`dbg_stall_i, dbg_dat_i, dbg_adr_i, dbg_op_i, dbg_ewt_i,`	`dbg_stall_i, dbg_dat_i, dbg_adr_i, dbg_op_i, dbg_ewt_i,`
`dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o, dbg_dat_o,`	`dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o, dbg_dat_o,`

`ifdef OR1200_BIST	`ifdef OR1200_BIST
`// RAM BIST`	`// RAM BIST`
`scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,`	`mbist_si_i, mbist_so_o, mbist_ctrl_i,`
`endif	`endif
`// Power Management`	`// Power Management`
`pm_cpustall_i,`	`pm_cpustall_i,`
`pm_clksd_o, pm_dc_gate_o, pm_ic_gate_o, pm_dmmu_gate_o,`	`pm_clksd_o, pm_dc_gate_o, pm_ic_gate_o, pm_dmmu_gate_o,`
`pm_immu_gate_o, pm_tt_gate_o, pm_cpu_gate_o, pm_wakeup_o, pm_lvolt_o`	`pm_immu_gate_o, pm_tt_gate_o, pm_cpu_gate_o, pm_wakeup_o, pm_lvolt_o`
Line 224...	Line 227...

`ifdef OR1200_BIST	`ifdef OR1200_BIST
`//`	`//`
`// RAM BIST`	`// RAM BIST`
`//`	`//`
`input scanb_rst,`	`input mbist_si_i;`
`scanb_si,`	input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
`scanb_en,`	`output mbist_so_o;`
`scanb_clk;`
`output scanb_so;`
`endif	`endif

`//`	`//`
`// Power Management`	`// Power Management`
`//`	`//`
Line 403...	Line 404...

`ifdef OR1200_BIST	`ifdef OR1200_BIST
`//`	`//`
`// RAM BIST`	`// RAM BIST`
`//`	`//`
`wire scanb_immu_so;`	`wire mbist_immu_so;`
`wire scanb_ic_so;`	`wire mbist_ic_so;`
`wire scanb_dmmu_so;`	`wire mbist_dmmu_so;`
`wire scanb_dc_so;`	`wire mbist_dc_so;`
`wire scanb_immu_si = scanb_si;`	`wire mbist_immu_si = mbist_si_i;`
`wire scanb_ic_si = scanb_immu_so;`	`wire mbist_ic_si = mbist_immu_so;`
`wire scanb_dmmu_si = scanb_ic_so;`	`wire mbist_dmmu_si = mbist_ic_so;`
`wire scanb_dc_si = scanb_dmmu_so;`	`wire mbist_dc_si = mbist_dmmu_so;`
`assign scanb_so = scanb_dc_so;`	`assign mbist_so_o = mbist_dc_so;`
`endif	`endif


`//`	`//`
`// Instantiation of Instruction WISHBONE BIU`	`// Instantiation of Instruction WISHBONE BIU`
Line 511...	Line 512...
`.clk(clk_i),`	`.clk(clk_i),`
`.rst(rst_i),`	`.rst(rst_i),`

`ifdef OR1200_BIST	`ifdef OR1200_BIST
`// RAM BIST`	`// RAM BIST`
`.scanb_rst(scanb_rst),`	`.mbist_si_i(mbist_immu_si),`
`.scanb_si(scanb_immu_si),`	`.mbist_so_o(mbist_immu_so),`
`.scanb_so(scanb_immu_so),`	`.mbist_ctrl_i(mbist_ctrl_i),`
`.scanb_en(scanb_en),`
`.scanb_clk(scanb_clk),`
`endif	`endif

`// CPU i/f`	`// CPU i/f`
`.ic_en(ic_en),`	`.ic_en(ic_en),`
`.immu_en(immu_en),`	`.immu_en(immu_en),`
Line 554...	Line 553...
`.clk(clk_i),`	`.clk(clk_i),`
`.rst(rst_i),`	`.rst(rst_i),`

`ifdef OR1200_BIST	`ifdef OR1200_BIST
`// RAM BIST`	`// RAM BIST`
`.scanb_rst(scanb_rst),`	`.mbist_si_i(mbist_ic_si),`
`.scanb_si(scanb_ic_si),`	`.mbist_so_o(mbist_ic_so),`
`.scanb_so(scanb_ic_so),`	`.mbist_ctrl_i(mbist_ctrl_i),`
`.scanb_en(scanb_en),`
`.scanb_clk(scanb_clk),`
`endif	`endif

`// IC and CPU/IMMU`	`// IC and CPU/IMMU`
`.ic_en(ic_en),`	`.ic_en(ic_en),`
`.icimmu_adr_i(icimmu_adr_immu),`	`.icimmu_adr_i(icimmu_adr_immu),`
Line 676...	Line 673...
`.clk(clk_i),`	`.clk(clk_i),`
`.rst(rst_i),`	`.rst(rst_i),`

`ifdef OR1200_BIST	`ifdef OR1200_BIST
`// RAM BIST`	`// RAM BIST`
`.scanb_rst(scanb_rst),`	`.mbist_si_i(mbist_dmmu_si),`
`.scanb_si(scanb_dmmu_si),`	`.mbist_so_o(mbist_dmmu_so),`
`.scanb_so(scanb_dmmu_so),`	`.mbist_ctrl_i(mbist_ctrl_i),`
`.scanb_en(scanb_en),`
`.scanb_clk(scanb_clk),`
`endif	`endif

`// CPU i/f`	`// CPU i/f`
`.dc_en(dc_en),`	`.dc_en(dc_en),`
`.dmmu_en(dmmu_en),`	`.dmmu_en(dmmu_en),`
Line 717...	Line 712...
`.clk(clk_i),`	`.clk(clk_i),`
`.rst(rst_i),`	`.rst(rst_i),`

`ifdef OR1200_BIST	`ifdef OR1200_BIST
`// RAM BIST`	`// RAM BIST`
`.scanb_rst(scanb_rst),`	`.mbist_si_i(mbist_dc_si),`
`.scanb_si(scanb_dc_si),`	`.mbist_so_o(mbist_dc_so),`
`.scanb_so(scanb_dc_so),`	`.mbist_ctrl_i(mbist_ctrl_i),`
`.scanb_en(scanb_en),`
`.scanb_clk(scanb_clk),`
`endif	`endif

`// DC and CPU/DMMU`	`// DC and CPU/DMMU`
`.dc_en(dc_en),`	`.dc_en(dc_en),`
`.dcdmmu_adr_i(dcdmmu_adr_dmmu),`	`.dcdmmu_adr_i(dcdmmu_adr_dmmu),`

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[/] [or1k/] [tags/] [rel_29/] [or1200/] [rtl/] [verilog/] [or1200_top.v] - Diff between revs 1104 and 1200