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Rev 788 |
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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// Revision 1.8 2001/10/21 17:57:16 lampret
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// Revision 1.8 2001/10/21 17:57:16 lampret
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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//
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//
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// Revision 1.7 2001/10/14 13:12:10 lampret
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// Revision 1.7 2001/10/14 13:12:10 lampret
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// MP3 version.
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// MP3 version.
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//
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//
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// Write-back multiplexer
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// Write-back multiplexer
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//
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//
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always @(muxin_a or muxin_b or muxin_c or muxin_d or rfwb_op) begin
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always @(muxin_a or muxin_b or muxin_c or muxin_d or rfwb_op) begin
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case(rfwb_op[`OR1200_RFWBOP_WIDTH-1:1]) // synopsys full_case parallel_case infer_mux
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`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
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case(rfwb_op[`OR1200_RFWBOP_WIDTH-1:1]) // synopsys parallel_case infer_mux
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`else
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case(rfwb_op[`OR1200_RFWBOP_WIDTH-1:1]) // synopsys parallel_case
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`endif
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2'b00: muxout = muxin_a;
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2'b00: muxout = muxin_a;
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2'b01: begin
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2'b01: begin
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muxout = muxin_b;
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muxout = muxin_b;
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`ifdef OR1200_VERBOSE
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`ifdef OR1200_VERBOSE
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// synopsys translate_off
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// synopsys translate_off
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