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Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1.1.1 2002/03/21 16:55:45 lampret
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// First import of the "new" XESS XSV environment.
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//
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//
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// Revision 1.5 2002/02/11 04:33:17 lampret
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// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
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//
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// Revision 1.4 2002/02/01 19:56:54 lampret
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// Revision 1.4 2002/02/01 19:56:54 lampret
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// Fixed combinational loops.
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// Fixed combinational loops.
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//
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//
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// Revision 1.3 2002/01/28 01:15:59 lampret
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// Revision 1.3 2002/01/28 01:15:59 lampret
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// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
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// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
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Line 208... |
Line 215... |
store <= #1 1'b0;
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store <= #1 1'b0;
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load <= #1 1'b1;
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load <= #1 1'b1;
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cache_inhibit <= #1 1'b0;
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cache_inhibit <= #1 1'b0;
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end
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end
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else begin // idle
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else begin // idle
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state <= #1 `OR1200_DCFSM_IDLE;
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hitmiss_eval <= #1 1'b0;
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hitmiss_eval <= #1 1'b0;
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store <= #1 1'b0;
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store <= #1 1'b0;
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load <= #1 1'b0;
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load <= #1 1'b0;
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cache_inhibit <= #1 1'b0;
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cache_inhibit <= #1 1'b0;
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end
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end
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`OR1200_DCFSM_CLOAD: begin // load
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`OR1200_DCFSM_CLOAD: begin // load
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if (dcdmmu_cycstb_i & dcdmmu_ci_i)
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if (dcdmmu_cycstb_i & dcdmmu_ci_i)
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cache_inhibit <= #1 1'b1;
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cache_inhibit <= #1 1'b1;
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if (hitmiss_eval)
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if (hitmiss_eval)
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saved_addr_r[31:13] <= #1 start_addr[31:13];
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saved_addr_r[31:13] <= #1 start_addr[31:13];
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if (!dc_en)
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if ((hitmiss_eval & !dcdmmu_cycstb_i) || // load aborted (usually caused by DMMU)
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state <= #1 `OR1200_DCFSM_IDLE;
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(biudata_error) || // load terminated with an error
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else if (hitmiss_eval & !dcdmmu_cycstb_i) begin // load aborted (usually caused by DMMU)
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((cache_inhibit | dcdmmu_ci_i) & biudata_valid)) begin // load from cache-inhibited area
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state <= #1 `OR1200_DCFSM_IDLE;
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hitmiss_eval <= #1 1'b0;
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load <= #1 1'b0;
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cache_inhibit <= #1 1'b0;
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end
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else if (biudata_error) begin // load terminated with an error
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state <= #1 `OR1200_DCFSM_IDLE;
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hitmiss_eval <= #1 1'b0;
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load <= #1 1'b0;
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cache_inhibit <= #1 1'b0;
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end
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else if ((cache_inhibit | dcdmmu_ci_i) & biudata_valid) begin // load from cache-inhibited area
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state <= #1 `OR1200_DCFSM_IDLE;
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state <= #1 `OR1200_DCFSM_IDLE;
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hitmiss_eval <= #1 1'b0;
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hitmiss_eval <= #1 1'b0;
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load <= #1 1'b0;
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load <= #1 1'b0;
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cache_inhibit <= #1 1'b0;
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cache_inhibit <= #1 1'b0;
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end
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end
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Line 256... |
Line 250... |
end
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end
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else // load in-progress
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else // load in-progress
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hitmiss_eval <= #1 1'b0;
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hitmiss_eval <= #1 1'b0;
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end
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end
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`OR1200_DCFSM_LREFILL3 : begin
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`OR1200_DCFSM_LREFILL3 : begin
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if (!dc_en)
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if (biudata_valid && (|cnt)) begin // refill ack, more loads to come
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state <= #1 `OR1200_DCFSM_IDLE;
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else if (biudata_valid && (|cnt)) begin // refill ack, more loads to come
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cnt <= #1 cnt - 'd1;
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cnt <= #1 cnt - 'd1;
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saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 'd1;
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saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 'd1;
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end
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end
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else if (biudata_valid) begin // last load of line refill
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else if (biudata_valid) begin // last load of line refill
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state <= #1 `OR1200_DCFSM_IDLE;
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state <= #1 `OR1200_DCFSM_IDLE;
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Line 272... |
Line 264... |
`OR1200_DCFSM_CSTORE: begin // store
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`OR1200_DCFSM_CSTORE: begin // store
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if (dcdmmu_cycstb_i & dcdmmu_ci_i)
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if (dcdmmu_cycstb_i & dcdmmu_ci_i)
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cache_inhibit <= #1 1'b1;
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cache_inhibit <= #1 1'b1;
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if (hitmiss_eval)
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if (hitmiss_eval)
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saved_addr_r[31:13] <= #1 start_addr[31:13];
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saved_addr_r[31:13] <= #1 start_addr[31:13];
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if (!dc_en)
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if ((hitmiss_eval & !dcdmmu_cycstb_i) || // store aborted (usually caused by DMMU)
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state <= #1 `OR1200_DCFSM_IDLE;
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(biudata_error) || // store terminated with an error
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else if (hitmiss_eval & !dcdmmu_cycstb_i) begin // store aborted (usually caused by DMMU)
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((cache_inhibit | dcdmmu_ci_i) & biudata_valid)) begin // store to cache-inhibited area
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state <= #1 `OR1200_DCFSM_IDLE;
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hitmiss_eval <= #1 1'b0;
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store <= #1 1'b0;
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cache_inhibit <= #1 1'b0;
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end
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else if (biudata_error) begin // store terminated with an error
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state <= #1 `OR1200_DCFSM_IDLE;
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hitmiss_eval <= #1 1'b0;
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store <= #1 1'b0;
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cache_inhibit <= #1 1'b0;
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end
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else if ((cache_inhibit | dcdmmu_ci_i) & biudata_valid) begin // store to cache-inhibited area
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state <= #1 `OR1200_DCFSM_IDLE;
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state <= #1 `OR1200_DCFSM_IDLE;
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hitmiss_eval <= #1 1'b0;
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hitmiss_eval <= #1 1'b0;
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store <= #1 1'b0;
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store <= #1 1'b0;
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cache_inhibit <= #1 1'b0;
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cache_inhibit <= #1 1'b0;
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end
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end
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Line 313... |
Line 293... |
else // store write-through in-progress
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else // store write-through in-progress
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hitmiss_eval <= #1 1'b0;
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hitmiss_eval <= #1 1'b0;
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end
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end
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`ifdef OR1200_DC_STORE_REFILL
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`ifdef OR1200_DC_STORE_REFILL
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`OR1200_DCFSM_SREFILL4 : begin
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`OR1200_DCFSM_SREFILL4 : begin
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if (!dc_en)
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if (biudata_valid && (|cnt)) begin // refill ack, more loads to come
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state <= #1 `OR1200_DCFSM_IDLE;
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else if (biudata_valid && (|cnt)) begin // refill ack, more loads to come
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cnt <= #1 cnt - 'd1;
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cnt <= #1 cnt - 'd1;
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saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 'd1;
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saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 'd1;
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end
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end
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else if (biudata_valid) begin // last load of line refill
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else if (biudata_valid) begin // last load of line refill
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state <= #1 `OR1200_DCFSM_IDLE;
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state <= #1 `OR1200_DCFSM_IDLE;
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