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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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// Revision 1.10 2001/11/13 10:02:21 lampret
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// Revision 1.10 2001/11/13 10:02:21 lampret
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// Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc)
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// Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc)
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//
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//
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// Revision 1.9 2001/10/21 17:57:16 lampret
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// Revision 1.9 2001/10/21 17:57:16 lampret
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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// Internal i/f
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// Internal i/f
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multicycle, flushpipe, extend_flush, lsu_stall, if_stall,
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multicycle, flushpipe, extend_flush, lsu_stall, if_stall,
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lsu_unstall, du_stall, mac_stall,
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lsu_unstall, du_stall, mac_stall,
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force_dslot_fetch,
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force_dslot_fetch,
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if_freeze, id_freeze, ex_freeze, wb_freeze
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genpc_freeze, if_freeze, id_freeze, ex_freeze, wb_freeze
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);
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);
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//
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//
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// I/O
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// I/O
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//
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//
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input if_stall;
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input if_stall;
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input lsu_unstall;
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input lsu_unstall;
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input force_dslot_fetch;
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input force_dslot_fetch;
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input du_stall;
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input du_stall;
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input mac_stall;
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input mac_stall;
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output genpc_freeze;
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output if_freeze;
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output if_freeze;
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output id_freeze;
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output id_freeze;
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output ex_freeze;
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output ex_freeze;
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output wb_freeze;
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output wb_freeze;
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//
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//
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// 2. Inserting NOPs in the middle of pipeline only if supported:
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// 2. Inserting NOPs in the middle of pipeline only if supported:
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// At this time, only ex_freeze (and wb_freeze) can be deassrted when id_freeze (and if_freeze) are asserted.
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// At this time, only ex_freeze (and wb_freeze) can be deassrted when id_freeze (and if_freeze) are asserted.
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// This way NOP is asserted from stage ID into EX stage.
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// This way NOP is asserted from stage ID into EX stage.
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//
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//
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assign genpc_freeze = du_stall | flushpipe;
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assign if_freeze = id_freeze | extend_flush;
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assign if_freeze = id_freeze | extend_flush;
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//assign id_freeze = (lsu_stall | (~lsu_unstall & if_stall) | multicycle_freeze | force_dslot_fetch) & ~flushpipe | du_stall;
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//assign id_freeze = (lsu_stall | (~lsu_unstall & if_stall) | multicycle_freeze | force_dslot_fetch) & ~flushpipe | du_stall;
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assign id_freeze = (lsu_stall | (~lsu_unstall & if_stall) | multicycle_freeze | force_dslot_fetch) | du_stall;
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assign id_freeze = (lsu_stall | (~lsu_unstall & if_stall) | multicycle_freeze | force_dslot_fetch) | du_stall;
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assign ex_freeze = wb_freeze;
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assign ex_freeze = wb_freeze;
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//assign wb_freeze = (lsu_stall | (~lsu_unstall & if_stall) | multicycle_freeze) & ~flushpipe | du_stall | mac_stall;
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//assign wb_freeze = (lsu_stall | (~lsu_unstall & if_stall) | multicycle_freeze) & ~flushpipe | du_stall | mac_stall;
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