URL
https://opencores.org/ocsvn/or1k/or1k/trunk
[/] [or1k/] [tags/] [rel_4/] [or1200/] [rtl/] [verilog/] [or1200_dpram_32x32.v] - Diff between revs 610 and 636
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
Rev 610 |
Rev 636 |
Line 59... |
Line 59... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.4 2002/01/23 07:52:36 lampret
|
|
// Changed default reset values for SR and ESR to match or1ksim's. Fixed flop model in or1200_dpram_32x32 when OR1200_XILINX_RAM32X1D is defined.
|
|
//
|
// Revision 1.3 2002/01/19 14:10:22 lampret
|
// Revision 1.3 2002/01/19 14:10:22 lampret
|
// Fixed OR1200_XILINX_RAM32X1D.
|
// Fixed OR1200_XILINX_RAM32X1D.
|
//
|
//
|
// Revision 1.2 2002/01/15 06:12:22 lampret
|
// Revision 1.2 2002/01/15 06:12:22 lampret
|
// Fixed module name when compiling with OR1200_XILINX_RAM32X1D
|
// Fixed module name when compiling with OR1200_XILINX_RAM32X1D
|
Line 218... |
Line 221... |
// Instantiation of ASIC memory:
|
// Instantiation of ASIC memory:
|
//
|
//
|
// Virtual Silicon Two-port R/W SRAM
|
// Virtual Silicon Two-port R/W SRAM
|
//
|
//
|
`ifdef UNUSED
|
`ifdef UNUSED
|
vs_hdtp_32x32 #(1<<aw, aw-1, dw-1) vs_ssp(
|
vs_hdtp_64x32 #(1<<aw, aw-1, dw-1) vs_ssp(
|
`else
|
`else
|
vs_hdtp_32x32 vs_ssp(
|
vs_hdtp_64x32 vs_ssp(
|
`endif
|
`endif
|
.RCK(clk_a),
|
.P1CK(clk_a),
|
.REN(~ce_a),
|
.P1CEN(~ce_a),
|
.OEN(~oe_a),
|
.P1WEN(1'b1),
|
.RADR(addr_a),
|
.P1OEN(~oe_a),
|
.DI(di_b),
|
.P1ADR({1'b0, addr_a}),
|
.WCK(clk_b),
|
.P1DI(32'h0000_0000),
|
.WEN(~ce_b),
|
.P1DOUT(do_a),
|
.WADR(addr_b),
|
|
.DOUT(do_a)
|
.P2CK(clk_b),
|
|
.P2CEN(~ce_b),
|
|
.P2WEN(~ce_b),
|
|
.P2OEN(1'b1),
|
|
.P2ADR({1'b0, addr_b}),
|
|
.P2DI(di_b),
|
|
.P2DOUT()
|
);
|
);
|
|
|
`else
|
`else
|
|
|
`ifdef OR1200_XILINX_RAM32X1D
|
`ifdef OR1200_XILINX_RAM32X1D
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.