| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2002/01/28 01:16:00 lampret
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// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
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//
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// Revision 1.2 2002/01/14 06:18:22 lampret
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// Revision 1.2 2002/01/14 06:18:22 lampret
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// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
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// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
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//
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//
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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| Line 89... |
Line 92... |
dcbiu_dat_o, dcbiu_adr_o, dcbiu_cyc_o, dcbiu_stb_o, dcbiu_we_o, dcbiu_sel_o, dcbiu_cab_o,
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dcbiu_dat_o, dcbiu_adr_o, dcbiu_cyc_o, dcbiu_stb_o, dcbiu_we_o, dcbiu_sel_o, dcbiu_cab_o,
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dcbiu_dat_i, dcbiu_ack_i, dcbiu_err_i,
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dcbiu_dat_i, dcbiu_ack_i, dcbiu_err_i,
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// Internal i/f
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// Internal i/f
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dc_en,
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dc_en,
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dcdmmu_adr_i, dcdmmu_cyc_i, dcdmmu_stb_i, dcdmmu_ci_i,
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dcdmmu_adr_i, dcdmmu_cycstb_i, dcdmmu_ci_i,
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dcpu_we_i, dcpu_sel_i, dcpu_tag_i, dcpu_dat_i,
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dcpu_we_i, dcpu_sel_i, dcpu_tag_i, dcpu_dat_i,
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dcpu_dat_o, dcpu_ack_o, dcpu_rty_o, dcdmmu_err_o, dcdmmu_tag_o,
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dcpu_dat_o, dcpu_ack_o, dcpu_rty_o, dcdmmu_err_o, dcdmmu_tag_o,
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// SPRs
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// SPRs
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spr_cs, spr_write, spr_dat_i
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spr_cs, spr_write, spr_dat_i
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| Line 128... |
Line 131... |
//
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//
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// Internal I/F
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// Internal I/F
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//
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//
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input dc_en;
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input dc_en;
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input [31:0] dcdmmu_adr_i;
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input [31:0] dcdmmu_adr_i;
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input dcdmmu_cyc_i;
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input dcdmmu_cycstb_i;
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input dcdmmu_stb_i;
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input dcdmmu_ci_i;
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input dcdmmu_ci_i;
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input dcpu_we_i;
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input dcpu_we_i;
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input [3:0] dcpu_sel_i;
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input [3:0] dcpu_sel_i;
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input [3:0] dcpu_tag_i;
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input [3:0] dcpu_tag_i;
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input [dw-1:0] dcpu_dat_i;
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input [dw-1:0] dcpu_dat_i;
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| Line 170... |
Line 172... |
wire dc_inv;
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wire dc_inv;
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wire dcfsm_first_hit_ack;
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wire dcfsm_first_hit_ack;
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wire dcfsm_first_miss_ack;
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wire dcfsm_first_miss_ack;
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wire dcfsm_first_miss_err;
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wire dcfsm_first_miss_err;
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wire dcfsm_burst;
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wire dcfsm_burst;
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wire dcfsm_tag_we;
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//
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//
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// Simple assignments
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// Simple assignments
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//
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//
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assign dcbiu_adr_o = dc_addr;
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assign dcbiu_adr_o = dc_addr;
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assign dc_inv = spr_cs & spr_write;
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assign dc_inv = spr_cs & spr_write;
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assign dctag_we = (dcfsm_biu_read & dcbiu_ack_i) | dc_inv;
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assign dctag_we = dcfsm_tag_we | dc_inv;
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assign dctag_addr = dc_inv ? spr_dat_i[`OR1200_DCINDXH:`OR1200_DCLS] : dc_addr[`OR1200_DCINDXH:`OR1200_DCLS];
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assign dctag_addr = dc_inv ? spr_dat_i[`OR1200_DCINDXH:`OR1200_DCLS] : dc_addr[`OR1200_DCINDXH:`OR1200_DCLS];
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assign dctag_en = dc_inv | dc_en;
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assign dctag_en = dc_inv | dc_en;
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assign dctag_v = ~dc_inv;
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assign dctag_v = ~dc_inv;
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//
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//
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| Line 190... |
Line 193... |
assign dcbiu_dat_o = dcpu_dat_i;
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assign dcbiu_dat_o = dcpu_dat_i;
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//
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//
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// Bypases of the DC when DC is disabled
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// Bypases of the DC when DC is disabled
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//
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//
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assign dcbiu_cyc_o = (dc_en) ? dcfsm_biu_read | dcfsm_biu_write : dcdmmu_cyc_i;
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assign dcbiu_cyc_o = (dc_en) ? dcfsm_biu_read | dcfsm_biu_write : dcdmmu_cycstb_i;
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assign dcbiu_stb_o = (dc_en) ? dcfsm_biu_read | dcfsm_biu_write : dcdmmu_stb_i;
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assign dcbiu_stb_o = (dc_en) ? dcfsm_biu_read | dcfsm_biu_write : dcdmmu_cycstb_i;
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assign dcbiu_we_o = (dc_en) ? dcfsm_biu_write : dcpu_we_i;
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assign dcbiu_we_o = (dc_en) ? dcfsm_biu_write : dcpu_we_i;
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assign dcbiu_sel_o = (dc_en & dcfsm_biu_read & !dcfsm_biu_write & !dcdmmu_ci_i) ? 4'b1111 : dcpu_sel_i;
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assign dcbiu_sel_o = (dc_en & dcfsm_biu_read & !dcfsm_biu_write & !dcdmmu_ci_i) ? 4'b1111 : dcpu_sel_i;
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assign dcbiu_cab_o = (dc_en) ? dcfsm_burst : 1'b0;
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assign dcbiu_cab_o = (dc_en) ? dcfsm_burst : 1'b0;
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assign dcpu_rty_o = ~dcpu_ack_o;
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assign dcpu_rty_o = ~dcpu_ack_o;
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assign dcdmmu_tag_o = dcdmmu_err_o ? `OR1200_DTAG_BE : dcpu_tag_i;
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assign dcdmmu_tag_o = dcdmmu_err_o ? `OR1200_DTAG_BE : dcpu_tag_i;
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| Line 207... |
Line 210... |
assign dcdmmu_err_o = dc_en ? dcfsm_first_miss_err : dcbiu_err_i;
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assign dcdmmu_err_o = dc_en ? dcfsm_first_miss_err : dcbiu_err_i;
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//
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//
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// Select between claddr generated by DC FSM and addr[3:2] generated by LSU
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// Select between claddr generated by DC FSM and addr[3:2] generated by LSU
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//
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//
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assign dc_addr = (dcfsm_biu_read | dcfsm_biu_write) ? saved_addr : dcdmmu_adr_i;
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//assign dc_addr = (dcfsm_biu_read | dcfsm_biu_write) ? saved_addr : dcdmmu_adr_i;
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//
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//
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// Select between input data generated by LSU or by BIU
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// Select between input data generated by LSU or by BIU
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//
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//
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assign to_dcram = (dcfsm_biu_read) ? dcbiu_dat_i : dcpu_dat_i;
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assign to_dcram = (dcfsm_biu_read) ? dcbiu_dat_i : dcpu_dat_i;
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| Line 236... |
Line 239... |
//
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//
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or1200_dc_fsm or1200_dc_fsm(
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or1200_dc_fsm or1200_dc_fsm(
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.clk(clk),
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.clk(clk),
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.rst(rst),
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.rst(rst),
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.dc_en(dc_en),
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.dc_en(dc_en),
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.dcdmmu_cyc_i(dcdmmu_cyc_i),
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.dcdmmu_cycstb_i(dcdmmu_cycstb_i),
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.dcdmmu_stb_i(dcdmmu_stb_i),
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.dcdmmu_ci_i(dcdmmu_ci_i),
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.dcdmmu_ci_i(dcdmmu_ci_i),
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.dcpu_we_i(dcpu_we_i),
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.dcpu_we_i(dcpu_we_i),
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.dcpu_sel_i(dcpu_sel_i),
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.dcpu_sel_i(dcpu_sel_i),
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.tagcomp_miss(tagcomp_miss),
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.tagcomp_miss(tagcomp_miss),
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.biudata_valid(dcbiu_ack_i),
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.biudata_valid(dcbiu_ack_i),
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| Line 252... |
Line 254... |
.biu_read(dcfsm_biu_read),
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.biu_read(dcfsm_biu_read),
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.biu_write(dcfsm_biu_write),
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.biu_write(dcfsm_biu_write),
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.first_hit_ack(dcfsm_first_hit_ack),
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.first_hit_ack(dcfsm_first_hit_ack),
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.first_miss_ack(dcfsm_first_miss_ack),
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.first_miss_ack(dcfsm_first_miss_ack),
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.first_miss_err(dcfsm_first_miss_err),
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.first_miss_err(dcfsm_first_miss_err),
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.burst(dcfsm_burst)
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.burst(dcfsm_burst),
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.tag_we(dcfsm_tag_we),
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.dc_addr(dc_addr)
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);
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);
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//
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//
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// Instantiation of DC main memory
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// Instantiation of DC main memory
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//
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//
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