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[/] [or1k/] [tags/] [rel_5/] [or1200/] [rtl/] [verilog/] [or1200_immu_tlb.v] - Diff between revs 660 and 958

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[/] [or1k/] [tags/] [rel_5/] [or1200/] [rtl/] [verilog/] [or1200_immu_tlb.v] - Diff between revs 660 and 958

Rev 660	Rev 958
Line 42...	Line 42...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.3 2002/02/11 04:33:17 lampret`
	`// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.`
	`//`
`// Revision 1.2 2002/01/28 01:16:00 lampret`	`// Revision 1.2 2002/01/28 01:16:00 lampret`
`// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.`	`// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.`
`//`	`//`
`// Revision 1.1 2002/01/03 08:16:15 lampret`	`// Revision 1.1 2002/01/03 08:16:15 lampret`
`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`	`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
Line 163...	Line 166...
assign tlb_tr_we = spr_cs & spr_write & spr_addr[`OR1200_ITLB_TM_ADDR];	assign tlb_tr_we = spr_cs & spr_write & spr_addr[`OR1200_ITLB_TM_ADDR];

`//`	`//`
`// Output to SPRS unit`	`// Output to SPRS unit`
`//`	`//`
assign spr_dat_o = (spr_cs & !spr_write & !spr_addr[`OR1200_ITLB_TM_ADDR]) ?	assign spr_dat_o = (!spr_write & !spr_addr[`OR1200_ITLB_TM_ADDR]) ?
{vpn, tlb_index & {`OR1200_ITLB_INDXW{v}}, {`OR1200_ITLB_TAGW-7{1'b0}}, 1'b0, 5'b00000, v} :	{vpn, tlb_index & {`OR1200_ITLB_INDXW{v}}, {`OR1200_ITLB_TAGW-7{1'b0}}, 1'b0, 5'b00000, v} :
(spr_cs & !spr_write & spr_addr[`OR1200_ITLB_TM_ADDR]) ?	(!spr_write & spr_addr[`OR1200_ITLB_TM_ADDR]) ?
{ppn, {`OR1200_IMMU_PS-8{1'b0}}, uxe, sxe, {4{1'b0}}, ci, 1'b0} :	{ppn, {`OR1200_IMMU_PS-8{1'b0}}, uxe, sxe, {4{1'b0}}, ci, 1'b0} :
`32'h00000000;`	`32'h00000000;`

`//`	`//`
`// Assign outputs from Match registers`	`// Assign outputs from Match registers`