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Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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// Revision 1.12 2001/11/23 21:42:31 simons
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// Revision 1.12 2001/11/23 21:42:31 simons
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// Program counter divided to PPC and NPC.
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// Program counter divided to PPC and NPC.
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//
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//
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// Revision 1.11 2001/11/23 08:38:51 lampret
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// Revision 1.11 2001/11/23 08:38:51 lampret
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// Changed DSR/DRR behavior and exception detection.
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// Changed DSR/DRR behavior and exception detection.
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Line 257... |
//
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//
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//
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//
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// What to write into SR
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// What to write into SR
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//
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//
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assign to_sr = (branch_op == `OR1200_BRANCHOP_RFE) ? esr : spr_dataout[`OR1200_SR_WIDTH-1:0];
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assign to_sr = (branch_op == `OR1200_BRANCHOP_RFE) ? esr : {1'b1, spr_dataout[`OR1200_SR_WIDTH-2:0]};
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//
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//
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// Selects for system SPRs
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// Selects for system SPRs
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//
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//
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assign cfgr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:4] == `OR1200_SPR_CFGR));
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assign cfgr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:4] == `OR1200_SPR_CFGR));
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//
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//
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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if (rst)
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if (rst)
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sr <= #1 `OR1200_SR_WIDTH'b011;
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sr <= #1 `OR1200_SR_WIDTH'b011;
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else if (except_started) begin
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else if (except_started) begin
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`ifdef OR1200_VERBOSE
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sr[`OR1200_SR_SM] <= #1 1'b1;
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// synopsys translate_off
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sr[`OR1200_SR_TEE] <= #1 1'b0;
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$display(" INFO: exception started. SR[SUPV] set and SR[EIR] cleared.");
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sr[`OR1200_SR_IEE] <= #1 1'b0;
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// synopsys translate_on
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`endif
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sr[`OR1200_SR_SUPV] <= #1 1'b1;
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sr[`OR1200_SR_EIR] <= #1 1'b0;
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sr[`OR1200_SR_DME] <= #1 1'b0;
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sr[`OR1200_SR_DME] <= #1 1'b0;
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sr[`OR1200_SR_IME] <= #1 1'b0;
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sr[`OR1200_SR_IME] <= #1 1'b0;
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end
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end
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else if (sr_we) begin
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else if (sr_we)
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`ifdef OR1200_VERBOSE
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sr <= #1 to_sr[`OR1200_SR_WIDTH-1:0];
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// synopsys translate_off
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else if (flag_we)
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$display(" INFO: writing into SR register: %h", spr_dataout);
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// synopsys translate_on
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`endif
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sr <= #1 {to_sr[`OR1200_SR_WIDTH-1:2], 1'b1, to_sr[0]};
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end
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else if (flag_we) begin
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`ifdef OR1200_VERBOSE
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// synopsys translate_off
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$display(" INFO: setting SR[F] bit: %b", flagforw);
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// synopsys translate_on
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`endif
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sr[`OR1200_SR_F] <= #1 flagforw;
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sr[`OR1200_SR_F] <= #1 flagforw;
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end
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//
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//
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// MTSPR/MFSPR interface
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// MTSPR/MFSPR interface
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//
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//
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always @(sprs_op or spr_addr or spr_dataout or sys_data or spr_dat_mac or spr_dat_pic or spr_dat_pm or
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always @(sprs_op or spr_addr or spr_dataout or sys_data or spr_dat_mac or spr_dat_pic or spr_dat_pm or
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