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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2002/01/28 01:16:00 lampret
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// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
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//
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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//
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// Revision 1.10 2001/11/13 10:00:49 lampret
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// Revision 1.10 2001/11/13 10:00:49 lampret
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// Fixed tick timer interrupt reporting by using TTCR[IP] bit.
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// Fixed tick timer interrupt reporting by using TTCR[IP] bit.
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// A match when TTMR[TP] is equal to TTCR[27:0]
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// A match when TTMR[TP] is equal to TTCR[27:0]
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//
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//
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assign match = (ttmr[`OR1200_TT_TTMR_TP] == ttcr[27:0]) ? 1'b1 : 1'b0;
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assign match = (ttmr[`OR1200_TT_TTMR_TP] == ttcr[27:0]) ? 1'b1 : 1'b0;
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//
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//
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// Restart when match and TTMR[M]==0x1 or when rst is asserted
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// Restart when match and TTMR[M]==0x1
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//
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//
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assign restart = (match && (ttmr[`OR1200_TT_TTMR_M] == 2'b01) || rst) ? 1'b1 : 1'b0;
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assign restart = match && (ttmr[`OR1200_TT_TTMR_M] == 2'b01);
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//
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//
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// Stop when match and TTMR[M]==0x2 or when TTMR[M]==0x0 or when RISC is stalled by debug unit
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// Stop when match and TTMR[M]==0x2 or when TTMR[M]==0x0 or when RISC is stalled by debug unit
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//
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//
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assign stop = match & (ttmr[`OR1200_TT_TTMR_M] == 2'b10) | (ttmr[`OR1200_TT_TTMR_M] == 2'b00) | du_stall;
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assign stop = match & (ttmr[`OR1200_TT_TTMR_M] == 2'b10) | (ttmr[`OR1200_TT_TTMR_M] == 2'b00) | du_stall;
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