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Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.20 2002/08/18 21:59:45 lampret
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// Disable SB until it is tested
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//
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// Revision 1.19 2002/08/18 19:53:08 lampret
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// Revision 1.19 2002/08/18 19:53:08 lampret
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// Added store buffer.
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// Added store buffer.
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//
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//
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// Revision 1.18 2002/08/15 06:04:11 lampret
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// Revision 1.18 2002/08/15 06:04:11 lampret
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// Fixed Xilinx trace buffer address. REported by Taylor Su.
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// Fixed Xilinx trace buffer address. REported by Taylor Su.
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Line 315... |
Line 318... |
// undefine this macro.
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// undefine this macro.
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//
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//
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//`define OR1200_WB_RETRY 7
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//`define OR1200_WB_RETRY 7
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//
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//
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// Store buffer
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//
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// It will improve performance by "caching" CPU stores
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// using store buffer. This is most important for function
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// prologues because DC can only work in write though mode
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// and all stores would have to complete external WB writes
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// to memory.
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// Store buffer is between DC and data BIU.
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// All stores will be stored into store buffer and immediately
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// completed by the CPU, even though actual external writes
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// will be performed later. As a consequence store buffer masks
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// all data bus errors related to stores (data bus errors
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// related to loads are delivered normally).
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// All pending CPU loads will wait until store buffer is empty to
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// ensure strict memory model. Right now this is necessary because
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// we don't make destinction between cached and cache inhibited
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// address space, so we simply empty store buffer until loads
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// can begin.
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//
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// [SB hasn't been tested yet, so don't enable it just yet!]
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//
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//`define OR1200_SB_IMPLEMENTED
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//
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// Enable additional synthesis directives if using
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// Enable additional synthesis directives if using
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// _Synopsys_ synthesis tool
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// _Synopsys_ synthesis tool
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//
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//
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//`define OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
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//`define OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
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Line 1232... |
Line 1211... |
`define OR1200_DCTAGL `OR1200_DCINDXH+1 // 13
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`define OR1200_DCTAGL `OR1200_DCINDXH+1 // 13
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`define OR1200_DCTAG `OR1200_DCSIZE-`OR1200_DCLS // 9
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`define OR1200_DCTAG `OR1200_DCSIZE-`OR1200_DCLS // 9
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`define OR1200_DCTAG_W 20
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`define OR1200_DCTAG_W 20
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`endif
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`endif
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No newline at end of file
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No newline at end of file
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/////////////////////////////////////////////////
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//
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// Store buffer (SB)
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//
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|
|
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//
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// Store buffer
|
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//
|
|
// It will improve performance by "caching" CPU stores
|
|
// using store buffer. This is most important for function
|
|
// prologues because DC can only work in write though mode
|
|
// and all stores would have to complete external WB writes
|
|
// to memory.
|
|
// Store buffer is between DC and data BIU.
|
|
// All stores will be stored into store buffer and immediately
|
|
// completed by the CPU, even though actual external writes
|
|
// will be performed later. As a consequence store buffer masks
|
|
// all data bus errors related to stores (data bus errors
|
|
// related to loads are delivered normally).
|
|
// All pending CPU loads will wait until store buffer is empty to
|
|
// ensure strict memory model. Right now this is necessary because
|
|
// we don't make destinction between cached and cache inhibited
|
|
// address space, so we simply empty store buffer until loads
|
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// can begin.
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//
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// It makes design a bit bigger, depending what is the number of
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// entries in SB FIFO. Number of entries can be changed further
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// down.
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//
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//`define OR1200_SB_IMPLEMENTED
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//
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// Number of store buffer entries
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//
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// Verified number of entries are 4 and 8 entries
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// (2 and 3 for OR1200_SB_LOG). OR1200_SB_ENTRIES must
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// always match 2**OR1200_SB_LOG.
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// To disable store buffer, undefine
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// OR1200_SB_IMPLEMENTED.
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//
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`define OR1200_SB_LOG 2 // 2 or 3
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`define OR1200_SB_ENTRIES 4 // 4 or 8
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No newline at end of file
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No newline at end of file
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