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// Revision 1.20  2002/08/18 21:59:45  lampret

// Disable SB until it is tested

//

/////////////////////////////////////////////////

//

// Store buffer (SB)

//

//

// Store buffer

//

// It will improve performance by "caching" CPU stores

// using store buffer. This is most important for function

// prologues because DC can only work in write though mode

// and all stores would have to complete external WB writes

// to memory.

// Store buffer is between DC and data BIU.

// All stores will be stored into store buffer and immediately

// completed by the CPU, even though actual external writes

// will be performed later. As a consequence store buffer masks

// all data bus errors related to stores (data bus errors

// related to loads are delivered normally).

// All pending CPU loads will wait until store buffer is empty to

// ensure strict memory model. Right now this is necessary because

// we don't make destinction between cached and cache inhibited

// address space, so we simply empty store buffer until loads

// can begin.

//

// It makes design a bit bigger, depending what is the number of

// entries in SB FIFO. Number of entries can be changed further

// down.

//

//`define OR1200_SB_IMPLEMENTED

//

// Number of store buffer entries

//

// Verified number of entries are 4 and 8 entries

// (2 and 3 for OR1200_SB_LOG). OR1200_SB_ENTRIES must

// always match 2**OR1200_SB_LOG.

// To disable store buffer, undefine

// OR1200_SB_IMPLEMENTED.

//

`define OR1200_SB_LOG           2       // 2 or 3

`define OR1200_SB_ENTRIES       4       // 4 or 8