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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2002/01/28 01:16:00 lampret
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// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
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//
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// Revision 1.2 2002/01/14 06:18:22 lampret
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// Revision 1.2 2002/01/14 06:18:22 lampret
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// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
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// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
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//
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//
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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Line 85... |
module or1200_dmmu_top(
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module or1200_dmmu_top(
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// Rst and clk
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// Rst and clk
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clk, rst,
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clk, rst,
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// CPU i/f
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// CPU i/f
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dc_en, dmmu_en, supv, dcpu_adr_i, dcpu_cyc_i, dcpu_stb_i, dcpu_we_i,
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dc_en, dmmu_en, supv, dcpu_adr_i, dcpu_cycstb_i, dcpu_we_i,
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dcpu_tag_o, dcpu_err_o,
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dcpu_tag_o, dcpu_err_o,
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// SPR access
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// SPR access
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spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
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spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
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// DC i/f
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// DC i/f
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dcdmmu_err_i, dcdmmu_tag_i, dcdmmu_adr_o, dcdmmu_cyc_o, dcdmmu_stb_o, dcdmmu_ci_o
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dcdmmu_err_i, dcdmmu_tag_i, dcdmmu_adr_o, dcdmmu_cycstb_o, dcdmmu_ci_o
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);
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);
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parameter dw = `OR1200_OPERAND_WIDTH;
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parameter dw = `OR1200_OPERAND_WIDTH;
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parameter aw = `OR1200_OPERAND_WIDTH;
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parameter aw = `OR1200_OPERAND_WIDTH;
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//
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//
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input dc_en;
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input dc_en;
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input dmmu_en;
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input dmmu_en;
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input supv;
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input supv;
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input [aw-1:0] dcpu_adr_i;
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input [aw-1:0] dcpu_adr_i;
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input dcpu_cyc_i;
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input dcpu_cycstb_i;
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input dcpu_stb_i;
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input dcpu_we_i;
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input dcpu_we_i;
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output [3:0] dcpu_tag_o;
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output [3:0] dcpu_tag_o;
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output dcpu_err_o;
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output dcpu_err_o;
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//
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//
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// DC I/F
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// DC I/F
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//
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//
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input dcdmmu_err_i;
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input dcdmmu_err_i;
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input [3:0] dcdmmu_tag_i;
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input [3:0] dcdmmu_tag_i;
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output [aw-1:0] dcdmmu_adr_o;
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output [aw-1:0] dcdmmu_adr_o;
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output dcdmmu_cyc_o;
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output dcdmmu_cycstb_o;
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output dcdmmu_stb_o;
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output dcdmmu_ci_o;
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output dcdmmu_ci_o;
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//
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//
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// Internal wires and regs
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// Internal wires and regs
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//
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//
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Line 154... |
wire dtlb_en;
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wire dtlb_en;
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wire dtlb_ci;
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wire dtlb_ci;
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reg dtlb_done;
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reg dtlb_done;
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wire fault;
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wire fault;
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wire miss;
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wire miss;
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reg [31:`OR1200_DMMU_PS] dcpu_vpn_r;
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//
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//
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// Implemented bits inside match and translate registers
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// Implemented bits inside match and translate registers
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//
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//
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// dtlbwYmrX: vpn 31-10 v 0
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// dtlbwYmrX: vpn 31-10 v 0
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// Put all outputs in inactive state
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// Put all outputs in inactive state
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//
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//
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assign spr_dat_o = 32'h00000000;
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assign spr_dat_o = 32'h00000000;
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assign dcdmmu_adr_o = dcpu_adr_i;
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assign dcdmmu_adr_o = dcpu_adr_i;
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assign dcpu_tag_o = dcdmmu_tag_i;
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assign dcpu_tag_o = dcdmmu_tag_i;
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assign dcdmmu_cyc_o = dcpu_cyc_i;
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assign dcdmmu_cyc_o = dcpu_cycstb_i;
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assign dcdmmu_stb_o = dcpu_stb_i;
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assign dcpu_err_o = dcdmmu_err_i;
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assign dcpu_err_o = dcdmmu_err_i;
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assign dcdmmu_ci_o = dcpu_adr_i[31];
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assign dcdmmu_ci_o = `OR1200_DMMU_CI;
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`else
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`else
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//
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//
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// DTLB SPR access
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// DTLB SPR access
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Line 214... |
//
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//
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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if (rst)
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if (rst)
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dtlb_done <= #1 1'b0;
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dtlb_done <= #1 1'b0;
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else if (dtlb_en)
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else if (dtlb_en)
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dtlb_done <= #1 dcpu_cyc_i;
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dtlb_done <= #1 dcpu_cycstb_i;
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else
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else
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dtlb_done <= #1 1'b0;
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dtlb_done <= #1 1'b0;
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//
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//
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// Cut transfer if something goes wrong with translation. If DC is disabled,
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// Cut transfer if something goes wrong with translation. Also delayed signals because of translation delay.
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// use delayed signals.
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//
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//
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assign dcdmmu_cyc_o = (!dc_en & dmmu_en) ? ~(miss | fault) & dtlb_done & dcpu_cyc_i : (miss | fault) ? 1'b0 : dcpu_cyc_i;
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assign dcdmmu_cycstb_o = (!dc_en & dmmu_en) ? ~(miss | fault) & dtlb_done & dcpu_cycstb_i : ~(miss | fault) & dcpu_cycstb_i;
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assign dcdmmu_stb_o = (!dc_en & dmmu_en) ? ~(miss | fault) & dtlb_done & dcpu_stb_i : (miss | fault) ? 1'b0 : dcpu_stb_i;
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//assign dcdmmu_cycstb_o = (dmmu_en) ? ~(miss | fault) & dcpu_cycstb_i : (miss | fault) ? 1'b0 : dcpu_cycstb_i;
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//
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//
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// Cache Inhibit
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// Cache Inhibit
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//
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//
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assign dcdmmu_ci_o = dmmu_en ? dtlb_done & dtlb_ci : dcpu_adr_i[31];
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assign dcdmmu_ci_o = dmmu_en ? dtlb_done & dtlb_ci : `OR1200_DMMU_CI;
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//
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// Register dcpu_adr_i's VPN for use when DMMU is not enabled but PPN is expected to come
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// one clock cycle after offset part.
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//
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always @(posedge clk or posedge rst)
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if (rst)
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dcpu_vpn_r <= #1 {31-`OR1200_DMMU_PS{1'b0}};
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else
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dcpu_vpn_r <= #1 dcpu_adr_i[31:`OR1200_DMMU_PS];
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//
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//
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// Physical address is either translated virtual address or
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// Physical address is either translated virtual address or
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// simply equal when DMMU is disabled
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// simply equal when DMMU is disabled
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//
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//
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// assign dcdmmu_adr_o = dmmu_en ? {dtlb_ppn, dcpu_adr_i[`OR1200_DMMU_PS-1:0]} : {dcpu_vpn_r, dcpu_adr_i[`OR1200_DMMU_PS-1:0]};
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assign dcdmmu_adr_o = dmmu_en ? {dtlb_ppn, dcpu_adr_i[`OR1200_DMMU_PS-1:0]} : dcpu_adr_i;
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assign dcdmmu_adr_o = dmmu_en ? {dtlb_ppn, dcpu_adr_i[`OR1200_DMMU_PS-1:0]} : dcpu_adr_i;
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//
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//
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// Output to SPRS unit
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// Output to SPRS unit
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//
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//
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Line 268... |
assign miss = dtlb_done & !dtlb_hit;
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assign miss = dtlb_done & !dtlb_hit;
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//
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//
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// DTLB Enable
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// DTLB Enable
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//
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//
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assign dtlb_en = dmmu_en & dcpu_cyc_i & dcpu_stb_i;
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assign dtlb_en = dmmu_en & dcpu_cycstb_i;
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//
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//
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// Instantiation of DTLB
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// Instantiation of DTLB
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//
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//
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or1200_dmmu_tlb or1200_dmmu_tlb(
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or1200_dmmu_tlb or1200_dmmu_tlb(
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