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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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// Revision 1.8 2001/10/21 17:57:16 lampret
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// Revision 1.8 2001/10/21 17:57:16 lampret
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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//
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//
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// Revision 1.7 2001/10/14 13:12:10 lampret
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// Revision 1.7 2001/10/14 13:12:10 lampret
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// MP3 version.
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// MP3 version.
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`include "or1200_defines.v"
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`include "or1200_defines.v"
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module or1200_pic(
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module or1200_pic(
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// RISC Internal Interface
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// RISC Internal Interface
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clk, rst, spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
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clk, rst, spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
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pic_wakeup, int_low, int_high,
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pic_wakeup, int,
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// PIC Interface
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// PIC Interface
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pic_int
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pic_int
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);
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);
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input spr_write; // SPR Write
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input spr_write; // SPR Write
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input [31:0] spr_addr; // SPR Address
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input [31:0] spr_addr; // SPR Address
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input [31:0] spr_dat_i; // SPR Write Data
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input [31:0] spr_dat_i; // SPR Write Data
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output [31:0] spr_dat_o; // SPR Read Data
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output [31:0] spr_dat_o; // SPR Read Data
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output pic_wakeup; // Wakeup to the PM
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output pic_wakeup; // Wakeup to the PM
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output int_low; // Low priority interrupt
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output int; // interrupt
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// exception request
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output int_high; // High priority interrupt
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// exception request
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// exception request
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//
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//
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// PIC Interface
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// PIC Interface
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//
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//
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Line 106... |
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`else
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`else
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wire [`OR1200_PIC_INTS-1:2] picmr; // No PICMR register
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wire [`OR1200_PIC_INTS-1:2] picmr; // No PICMR register
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`endif
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`endif
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//
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//
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// PIC Priority Register bits (or no register)
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//
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`ifdef OR1200_PIC_PICPR
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reg [`OR1200_PIC_INTS-1:2] picpr; // PICPR bits
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`else
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wire [`OR1200_PIC_INTS-1:2] picpr; // No PICPR register
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`endif
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//
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// PIC Status Register bits (or no register)
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// PIC Status Register bits (or no register)
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//
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//
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`ifdef OR1200_PIC_PICSR
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`ifdef OR1200_PIC_PICSR
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reg [`OR1200_PIC_INTS-1:0] picsr; // PICSR bits
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reg [`OR1200_PIC_INTS-1:0] picsr; // PICSR bits
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`else
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`else
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Line 119... |
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//
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//
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// Internal wires & regs
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// Internal wires & regs
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//
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//
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wire picmr_sel; // PICMR select
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wire picmr_sel; // PICMR select
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wire picpr_sel; // PICPR select
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wire picsr_sel; // PICSR select
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wire picsr_sel; // PICSR select
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wire [`OR1200_PIC_INTS-1:0] um_ints;// Unmasked interrupts
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wire [`OR1200_PIC_INTS-1:0] um_ints;// Unmasked interrupts
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reg [31:0] spr_dat_o; // SPR data out
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reg [31:0] spr_dat_o; // SPR data out
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//
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//
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// PIC registers address decoder
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// PIC registers address decoder
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//
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//
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assign picmr_sel = (spr_cs && (spr_addr[`OR1200_PICOFS_BITS] == `OR1200_PIC_OFS_PICMR)) ? 1'b1 : 1'b0;
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assign picmr_sel = (spr_cs && (spr_addr[`OR1200_PICOFS_BITS] == `OR1200_PIC_OFS_PICMR)) ? 1'b1 : 1'b0;
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assign picpr_sel = (spr_cs && (spr_addr[`OR1200_PICOFS_BITS] == `OR1200_PIC_OFS_PICPR)) ? 1'b1 : 1'b0;
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assign picsr_sel = (spr_cs && (spr_addr[`OR1200_PICOFS_BITS] == `OR1200_PIC_OFS_PICSR)) ? 1'b1 : 1'b0;
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assign picsr_sel = (spr_cs && (spr_addr[`OR1200_PICOFS_BITS] == `OR1200_PIC_OFS_PICSR)) ? 1'b1 : 1'b0;
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//
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//
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// Write to PICMR
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// Write to PICMR
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//
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//
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`ifdef OR1200_PIC_PICMR
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`ifdef OR1200_PIC_PICMR
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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if (rst)
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if (rst)
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// picmr <= {`OR1200_PIC_INTS-2{1'b0}};
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picmr <= {1'b1, {`OR1200_PIC_INTS-3{1'b0}}};
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picmr <= {1'b1, {`OR1200_PIC_INTS-3{1'b0}}};
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else if (picmr_sel && spr_write) begin
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else if (picmr_sel && spr_write) begin
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picmr <= #1 spr_dat_i[`OR1200_PIC_INTS-1:2];
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picmr <= #1 spr_dat_i[`OR1200_PIC_INTS-1:2];
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end
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end
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`else
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`else
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assign picpr = (`OR1200_PIC_INTS)'b1;
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assign picmr = (`OR1200_PIC_INTS)'b1;
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`endif
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//
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// Write to PICPR
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//
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`ifdef OR1200_PIC_PICPR
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always @(posedge clk or posedge rst)
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if (rst)
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picpr <= {`OR1200_PIC_INTS-2{1'b0}};
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else if (picpr_sel && spr_write) begin
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picpr <= #1 spr_dat_i[`OR1200_PIC_INTS-1:2];
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end
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`else
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assign picpr = 0;
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`endif
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`endif
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//
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//
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// Write to PICSR, both CPU and external ints
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// Write to PICSR, both CPU and external ints
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//
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//
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Line 161... |
`endif
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`endif
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//
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//
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// Read PIC registers
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// Read PIC registers
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//
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//
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always @(spr_addr or picmr or picpr or picsr)
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always @(spr_addr or picmr or picsr)
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case (spr_addr[`OR1200_PICOFS_BITS]) // synopsys full_case parallel_case
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case (spr_addr[`OR1200_PICOFS_BITS]) // synopsys full_case parallel_case
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`ifdef OR1200_PIC_READREGS
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`ifdef OR1200_PIC_READREGS
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`OR1200_PIC_OFS_PICMR: begin
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`OR1200_PIC_OFS_PICMR: begin
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spr_dat_o[`OR1200_PIC_INTS-1:0] = {picmr, 2'b0};
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spr_dat_o[`OR1200_PIC_INTS-1:0] = {picmr, 2'b0};
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`ifdef OR1200_PIC_UNUSED_ZERO
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`ifdef OR1200_PIC_UNUSED_ZERO
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spr_dat_o[31:`OR1200_PIC_INTS] = {32-`OR1200_PIC_INTS{1'b0}};
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spr_dat_o[31:`OR1200_PIC_INTS] = {32-`OR1200_PIC_INTS{1'b0}};
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`endif
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`endif
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end
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end
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`OR1200_PIC_OFS_PICPR: begin
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spr_dat_o[`OR1200_PIC_INTS-1:0] = {picpr, 2'b0};
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`ifdef OR1200_PIC_UNUSED_ZERO
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spr_dat_o[31:`OR1200_PIC_INTS] = {32-`OR1200_PIC_INTS{1'b0}};
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`endif
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end
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`endif
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`endif
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default: begin
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default: begin
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spr_dat_o[`OR1200_PIC_INTS-1:0] = picsr;
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spr_dat_o[`OR1200_PIC_INTS-1:0] = picsr;
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`ifdef OR1200_PIC_UNUSED_ZERO
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`ifdef OR1200_PIC_UNUSED_ZERO
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spr_dat_o[31:`OR1200_PIC_INTS] = {32-`OR1200_PIC_INTS{1'b0}};
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spr_dat_o[31:`OR1200_PIC_INTS] = {32-`OR1200_PIC_INTS{1'b0}};
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Line 185... |
// Unmasked interrupts
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// Unmasked interrupts
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//
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//
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assign um_ints = pic_int & {picmr, 2'b11};
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assign um_ints = pic_int & {picmr, 2'b11};
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//
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//
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// Generate int_low
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// Generate int
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//
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assign int_low = (um_ints & {~picpr, 2'b10}) ? 1'b1 : 1'b0;
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//
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// Generate int_high
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//
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//
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assign int_high = (um_ints & {picpr, 2'b01}) ? 1'b1 : 1'b0;
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assign int = |um_ints;
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//
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//
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// Assert pic_wakeup when either intlow or int_high is asserted
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// Assert pic_wakeup when int is asserted
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//
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//
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assign pic_wakeup = int_low | int_high;
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assign pic_wakeup = int;
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`else
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`else
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//
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//
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// When PIC is not implemented, drive all outputs as would when PIC is disabled
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// When PIC is not implemented, drive all outputs as would when PIC is disabled
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//
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//
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assign int_low = pic_int[1];
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assign int = pic_int[1] | pic_int[0];
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assign int_high = pic_int[0];
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assign pic_wakeup= int;
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assign pic_wakeup= int_low | int_high;
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//
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//
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// Read PIC registers
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// Read PIC registers
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//
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//
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`ifdef OR1200_PIC_READREGS
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`ifdef OR1200_PIC_READREGS
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