| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2002/01/18 07:56:00 lampret
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// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
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//
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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//
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// Revision 1.13 2001/11/23 08:38:51 lampret
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// Revision 1.13 2001/11/23 08:38:51 lampret
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// Changed DSR/DRR behavior and exception detection.
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// Changed DSR/DRR behavior and exception detection.
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| Line 276... |
Line 279... |
wire icpu_we_cpu;
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wire icpu_we_cpu;
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wire [3:0] icpu_sel_cpu;
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wire [3:0] icpu_sel_cpu;
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wire [3:0] icpu_tag_cpu;
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wire [3:0] icpu_tag_cpu;
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wire [31:0] icpu_dat_ic;
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wire [31:0] icpu_dat_ic;
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wire icpu_ack_ic;
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wire icpu_ack_ic;
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wire icpu_rty_ic;
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wire [31:0] icpu_adr_immu;
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wire [31:0] icpu_adr_immu;
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wire icpu_err_immu;
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wire icpu_err_immu;
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wire [3:0] icpu_tag_immu;
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wire [3:0] icpu_tag_immu;
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//
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//
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// IMMU and IC
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// IMMU and IC
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//
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//
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wire [aw-1:0] icimmu_adr_immu;
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wire [aw-1:0] icimmu_adr_immu;
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wire icimmu_rty_ic;
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wire icimmu_err_ic;
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wire icimmu_err_ic;
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wire [3:0] icimmu_tag_ic;
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wire [3:0] icimmu_tag_ic;
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wire icimmu_cyc_immu;
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wire icimmu_cyc_immu;
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wire icimmu_stb_immu;
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wire icimmu_stb_immu;
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wire icimmu_ci_immu;
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wire icimmu_ci_immu;
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| Line 417... |
Line 420... |
.icpu_adr_i(icpu_adr_cpu),
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.icpu_adr_i(icpu_adr_cpu),
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.icpu_cyc_i(icpu_cyc_cpu),
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.icpu_cyc_i(icpu_cyc_cpu),
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.icpu_stb_i(icpu_stb_cpu),
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.icpu_stb_i(icpu_stb_cpu),
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.icpu_adr_o(icpu_adr_immu),
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.icpu_adr_o(icpu_adr_immu),
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.icpu_tag_o(icpu_tag_immu),
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.icpu_tag_o(icpu_tag_immu),
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.icpu_rty_o(icpu_rty_immu),
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.icpu_err_o(icpu_err_immu),
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.icpu_err_o(icpu_err_immu),
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// SPR access
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// SPR access
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.spr_cs(spr_cs[`OR1200_SPR_GROUP_IMMU]),
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.spr_cs(spr_cs[`OR1200_SPR_GROUP_IMMU]),
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.spr_write(spr_we),
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.spr_write(spr_we),
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.spr_addr(spr_addr),
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.spr_addr(spr_addr),
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.spr_dat_i(spr_dat_cpu),
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.spr_dat_i(spr_dat_cpu),
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.spr_dat_o(spr_dat_immu),
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.spr_dat_o(spr_dat_immu),
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// IC i/f
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// IC i/f
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.icimmu_rty_i(icimmu_rty_ic),
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.icimmu_err_i(icimmu_err_ic),
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.icimmu_err_i(icimmu_err_ic),
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.icimmu_tag_i(icimmu_tag_ic),
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.icimmu_tag_i(icimmu_tag_ic),
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.icimmu_adr_o(icimmu_adr_immu),
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.icimmu_adr_o(icimmu_adr_immu),
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.icimmu_cyc_o(icimmu_cyc_immu),
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.icimmu_cyc_o(icimmu_cyc_immu),
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.icimmu_stb_o(icimmu_stb_immu),
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.icimmu_stb_o(icimmu_stb_immu),
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| Line 453... |
Line 458... |
.icpu_we_i(icpu_we_cpu),
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.icpu_we_i(icpu_we_cpu),
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.icpu_sel_i(icpu_sel_cpu),
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.icpu_sel_i(icpu_sel_cpu),
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.icpu_tag_i(icpu_tag_cpu),
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.icpu_tag_i(icpu_tag_cpu),
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.icpu_dat_o(icpu_dat_ic),
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.icpu_dat_o(icpu_dat_ic),
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.icpu_ack_o(icpu_ack_ic),
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.icpu_ack_o(icpu_ack_ic),
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.icpu_rty_o(icpu_rty_ic),
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.icimmu_rty_o(icimmu_rty_ic),
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.icimmu_err_o(icimmu_err_ic),
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.icimmu_err_o(icimmu_err_ic),
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.icimmu_tag_o(icimmu_tag_ic),
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.icimmu_tag_o(icimmu_tag_ic),
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// SPR access
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// SPR access
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.spr_cs(spr_cs[`OR1200_SPR_GROUP_IC]),
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.spr_cs(spr_cs[`OR1200_SPR_GROUP_IC]),
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| Line 492... |
Line 497... |
.icpu_we_o(icpu_we_cpu),
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.icpu_we_o(icpu_we_cpu),
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.icpu_sel_o(icpu_sel_cpu),
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.icpu_sel_o(icpu_sel_cpu),
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.icpu_tag_o(icpu_tag_cpu),
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.icpu_tag_o(icpu_tag_cpu),
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.icpu_dat_i(icpu_dat_ic),
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.icpu_dat_i(icpu_dat_ic),
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.icpu_ack_i(icpu_ack_ic),
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.icpu_ack_i(icpu_ack_ic),
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.icpu_rty_i(icpu_rty_ic),
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.icpu_rty_i(icpu_rty_immu),
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.icpu_adr_i(icpu_adr_immu),
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.icpu_adr_i(icpu_adr_immu),
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.icpu_err_i(icpu_err_immu),
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.icpu_err_i(icpu_err_immu),
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.icpu_tag_i(icpu_tag_immu),
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.icpu_tag_i(icpu_tag_immu),
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// Connection CPU to external Debug port
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// Connection CPU to external Debug port
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| Line 696... |
Line 701... |
//
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//
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or1200_tt or1200_tt(
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or1200_tt or1200_tt(
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// RISC Internal Interface
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// RISC Internal Interface
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.clk(clk_i),
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.clk(clk_i),
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.rst(rst_i),
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.rst(rst_i),
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.du_stall(du_stall),
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.spr_cs(spr_cs[`OR1200_SPR_GROUP_TT]),
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.spr_cs(spr_cs[`OR1200_SPR_GROUP_TT]),
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.spr_write(spr_we),
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.spr_write(spr_we),
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.spr_addr(spr_addr),
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.spr_addr(spr_addr),
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.spr_dat_i(spr_dat_cpu),
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.spr_dat_i(spr_dat_cpu),
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.spr_dat_o(spr_dat_tt),
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.spr_dat_o(spr_dat_tt),
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