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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2002/07/14 22:17:17 lampret
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// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.
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//
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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//
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// Revision 1.12 2001/11/22 13:42:51 lampret
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// Revision 1.12 2001/11/22 13:42:51 lampret
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// Added wb_cyc_o assignment after it was removed by accident.
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// Added wb_cyc_o assignment after it was removed by accident.
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| Line 154... |
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reg [dw-1:0] biu_dat_o; // output data bus
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reg [dw-1:0] biu_dat_o; // output data bus
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`else
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`else
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wire long_ack_o; // normal termination
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wire long_ack_o; // normal termination
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wire long_err_o; // error termination
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wire long_err_o; // error termination
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`endif
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`endif
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wire aborted; // Graceful abort
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reg aborted_r; // Graceful abort
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wire retry; // Retry
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`ifdef OR1200_WB_RETRY
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reg [`OR1200_WB_RETRY-1:0] retry_cntr; // Retry counter
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`endif
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//
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//
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// WISHBONE I/F <-> Internal RISC I/F conversion
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// WISHBONE I/F <-> Internal RISC I/F conversion
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//
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//
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Line 175... |
//
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//
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`ifdef OR1200_REGISTERED_OUTPUTS
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`ifdef OR1200_REGISTERED_OUTPUTS
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always @(posedge wb_clk_i or posedge wb_rst_i)
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always @(posedge wb_clk_i or posedge wb_rst_i)
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if (wb_rst_i)
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if (wb_rst_i)
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wb_adr_o <= #1 {aw{1'b0}};
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wb_adr_o <= #1 {aw{1'b0}};
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else if ((biu_cyc_i & biu_stb_i) & ~wb_ack_i)
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else if ((biu_cyc_i & biu_stb_i) & ~wb_ack_i & ~aborted & ~(wb_stb_o & ~wb_ack_i))
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wb_adr_o <= #1 biu_adr_i;
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wb_adr_o <= #1 biu_adr_i;
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`else
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`else
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assign wb_adr_o = biu_adr_i;
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assign wb_adr_o = biu_adr_i;
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`endif
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`endif
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Line 201... |
//
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//
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`ifdef OR1200_REGISTERED_OUTPUTS
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`ifdef OR1200_REGISTERED_OUTPUTS
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always @(posedge wb_clk_i or posedge wb_rst_i)
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always @(posedge wb_clk_i or posedge wb_rst_i)
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if (wb_rst_i)
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if (wb_rst_i)
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wb_dat_o <= #1 {dw{1'b0}};
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wb_dat_o <= #1 {dw{1'b0}};
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else if ((biu_cyc_i & biu_stb_i) & ~wb_ack_i)
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else if ((biu_cyc_i & biu_stb_i) & ~wb_ack_i & ~aborted)
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wb_dat_o <= #1 biu_dat_i;
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wb_dat_o <= #1 biu_dat_i;
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`else
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`else
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assign wb_dat_o = biu_dat_i;
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assign wb_dat_o = biu_dat_i;
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`endif
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`endif
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`ifdef OR1200_REGISTERED_INPUTS
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`ifdef OR1200_REGISTERED_INPUTS
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always @(posedge wb_clk_i or posedge wb_rst_i)
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always @(posedge wb_clk_i or posedge wb_rst_i)
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if (wb_rst_i)
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if (wb_rst_i)
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long_ack_o <= #1 1'b0;
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long_ack_o <= #1 1'b0;
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else
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else
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long_ack_o <= #1 wb_ack_i;
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long_ack_o <= #1 wb_ack_i & ~aborted;
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`else
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`else
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assign long_ack_o = wb_ack_i;
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assign long_ack_o = wb_ack_i & ~aborted;
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`endif
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`endif
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//
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//
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// biu_err_o is one RISC clock cycle long long_err_o.
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// biu_err_o is one RISC clock cycle long long_err_o.
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// long_err_o is one, two or four RISC clock cycles long because
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// long_err_o is one, two or four RISC clock cycles long because
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Line 271... |
`ifdef OR1200_REGISTERED_INPUTS
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`ifdef OR1200_REGISTERED_INPUTS
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always @(posedge wb_clk_i or posedge wb_rst_i)
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always @(posedge wb_clk_i or posedge wb_rst_i)
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if (wb_rst_i)
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if (wb_rst_i)
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long_err_o <= #1 1'b0;
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long_err_o <= #1 1'b0;
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else
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else
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long_err_o <= #1 wb_err_i;
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long_err_o <= #1 wb_err_i & ~aborted;
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`else
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`else
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assign long_err_o = wb_err_i;
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assign long_err_o = wb_err_i & ~aborted;
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`endif
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`endif
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//
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//
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// Retry counter
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//
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// Assert 'retry' when 'wb_rty_i' is sampled high and keep it high
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// until retry counter doesn't expire
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//
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`ifdef OR1200_WB_RETRY
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assign retry = wb_rty_i | (|retry_cntr);
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`else
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assign retry = 1'b0;
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`endif
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`ifdef OR1200_WB_RETRY
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always @(posedge wb_clk_i or posedge wb_rst_i)
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if (wb_rst_i)
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retry_cntr <= #1 1'b0;
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else if (wb_rty_i)
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retry_cntr <= #1 {`OR1200_WB_RETRY{1'b1}};
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else if (retry_cntr)
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retry_cntr <= #1 retry_cntr - 7'd1;
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`endif
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//
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// Graceful completion of aborted transfers
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//
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// Assert 'aborted' when 1) current transfer is in progress (wb_stb_o; which
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// we know is only asserted together with wb_cyc_o) 2) and in next WB clock cycle
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// wb_stb_o would be deasserted (biu_cyc_i and biu_stb_i are low) 3) and
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// there is no termination of current transfer in this WB clock cycle (wb_ack_i
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// and wb_err_i are low).
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// Extend 'aborted' signal with 'aborted_r' until this "aborted" transfer
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// is properly terminated with wb_ack_i/wb_err_i.
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//
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//
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assign aborted = wb_stb_o & ~(biu_cyc_i & biu_stb_i) & ~(wb_ack_i | wb_err_i) | aborted_r;
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always @(posedge wb_clk_i or posedge wb_rst_i)
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if (wb_rst_i)
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aborted_r <= #1 1'b0;
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else if (wb_ack_i | wb_err_i)
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aborted_r <= #1 1'b0;
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else if (aborted)
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aborted_r <= #1 1'b1;
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//
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// WB cyc_o
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// WB cyc_o
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//
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//
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// Either 1) normal transfer initiated by biu_cyc_i (and biu_cab_i if
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// bursts are enabled) and possibly suspended by 'retry'
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// or 2) extended "aborted" transfer
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//
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`ifdef OR1200_REGISTERED_OUTPUTS
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`ifdef OR1200_REGISTERED_OUTPUTS
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always @(posedge wb_clk_i or posedge wb_rst_i)
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always @(posedge wb_clk_i or posedge wb_rst_i)
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if (wb_rst_i)
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if (wb_rst_i)
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wb_cyc_o <= #1 1'b0;
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wb_cyc_o <= #1 1'b0;
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else
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else
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`ifdef OR1200_NO_BURSTS
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`ifdef OR1200_NO_BURSTS
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wb_cyc_o <= #1 biu_cyc_i & ~wb_ack_i;
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wb_cyc_o <= #1 biu_cyc_i & ~wb_ack_i & ~retry | aborted & ~wb_ack_i;
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`else
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`else
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wb_cyc_o <= #1 biu_cyc_i & ~wb_ack_i | biu_cab_i;
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wb_cyc_o <= #1 biu_cyc_i & ~wb_ack_i & ~retry | biu_cab_i | aborted & ~wb_ack_i;
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`endif
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`endif
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`else
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`else
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`ifdef OR1200_NO_BURSTS
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`ifdef OR1200_NO_BURSTS
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assign wb_cyc_o = biu_cyc_i;
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assign wb_cyc_o = biu_cyc_i & ~retry;
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`else
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`else
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assign wb_cyc_o = biu_cyc_i | biu_cab_i;
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assign wb_cyc_o = biu_cyc_i | biu_cab_i & ~retry;
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`endif
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`endif
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`endif
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`endif
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//
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//
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// WB stb_o
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// WB stb_o
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Line 351... |
`ifdef OR1200_REGISTERED_OUTPUTS
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`ifdef OR1200_REGISTERED_OUTPUTS
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always @(posedge wb_clk_i or posedge wb_rst_i)
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always @(posedge wb_clk_i or posedge wb_rst_i)
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if (wb_rst_i)
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if (wb_rst_i)
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wb_stb_o <= #1 1'b0;
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wb_stb_o <= #1 1'b0;
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else
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else
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wb_stb_o <= #1 (biu_cyc_i & biu_stb_i) & ~wb_ack_i;
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wb_stb_o <= #1 (biu_cyc_i & biu_stb_i) & ~wb_ack_i & ~retry | aborted & ~wb_ack_i;
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`else
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`else
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assign wb_stb_o = biu_cyc_i & biu_stb_i;
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assign wb_stb_o = biu_cyc_i & biu_stb_i;
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`endif
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`endif
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//
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//
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| Line 309... |
Line 364... |
`ifdef OR1200_REGISTERED_OUTPUTS
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`ifdef OR1200_REGISTERED_OUTPUTS
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always @(posedge wb_clk_i or posedge wb_rst_i)
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always @(posedge wb_clk_i or posedge wb_rst_i)
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if (wb_rst_i)
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if (wb_rst_i)
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wb_we_o <= #1 1'b0;
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wb_we_o <= #1 1'b0;
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else
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else
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wb_we_o <= #1 biu_cyc_i & biu_stb_i & biu_we_i;
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wb_we_o <= #1 biu_cyc_i & biu_stb_i & biu_we_i | aborted & wb_we_o;
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`else
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`else
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assign wb_we_o = biu_cyc_i & biu_stb_i & biu_we_i;
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assign wb_we_o = biu_cyc_i & biu_stb_i & biu_we_i;
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`endif
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`endif
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//
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//
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