| Line 111... |
Line 111... |
value |= UART_FCR_RRXFI | UART_FCR_RTXFI;
|
value |= UART_FCR_RRXFI | UART_FCR_RTXFI;
|
uarts[chipsel].fifo_len = (value & UART_FCR_FIE) ? 16 : 1;
|
uarts[chipsel].fifo_len = (value & UART_FCR_FIE) ? 16 : 1;
|
if (value & UART_FCR_RTXFI) {
|
if (value & UART_FCR_RTXFI) {
|
uarts[chipsel].istat.txbuf_head = uarts[chipsel].istat.txbuf_tail = 0;
|
uarts[chipsel].istat.txbuf_head = uarts[chipsel].istat.txbuf_tail = 0;
|
uarts[chipsel].istat.txbuf_full = 0;
|
uarts[chipsel].istat.txbuf_full = 0;
|
uarts[chipsel].regs.lsr &= ~UART_LSR_TXBUFE;
|
uarts[chipsel].regs.lsr |= UART_LSR_TXBUFE;
|
uarts[chipsel].istat.thre_int = 0;
|
|
|
// For FIFO-mode only, THRE interrupt is set when THR and FIFO are empty
|
|
uarts[chipsel].istat.thre_int = (uarts[chipsel].fifo_len == 16);
|
}
|
}
|
if (value & UART_FCR_RRXFI) {
|
if (value & UART_FCR_RRXFI) {
|
uarts[chipsel].istat.rxbuf_head = uarts[chipsel].istat.rxbuf_tail = 0;
|
uarts[chipsel].istat.rxbuf_head = uarts[chipsel].istat.rxbuf_tail = 0;
|
uarts[chipsel].istat.rxbuf_full = 0;
|
uarts[chipsel].istat.rxbuf_full = 0;
|
uarts[chipsel].regs.lsr &= ~UART_LSR_RDRDY;
|
uarts[chipsel].regs.lsr &= ~UART_LSR_RDRDY;
|
| Line 392... |
Line 394... |
} else
|
} else
|
uarts[i].vapi.break_sent = 0;
|
uarts[i].vapi.break_sent = 0;
|
|
|
}
|
}
|
|
|
// For FIFO-mode only, THRE interrupt is set when THR and FIFO are empty
|
|
if (!uarts[i].istat.txbuf_full && (uarts[i].fifo_len == 16)) {
|
|
uarts[i].regs.lsr |= UART_LSR_TXBUFE;
|
|
uarts[i].istat.thre_int = 1;
|
|
}
|
|
|
|
/***************** Receive *****************/
|
/***************** Receive *****************/
|
|
|
/* Is there a break? */
|
/* Is there a break? */
|
if (uarts[i].vapi.cur_break) {
|
if (uarts[i].vapi.cur_break) {
|
uarts[i].vapi.cur_break_cnt++;
|
uarts[i].vapi.cur_break_cnt++;
|
| Line 608... |
Line 604... |
uarts[i].istat.rxbuf_head = uarts[i].istat.rxbuf_tail = 0;
|
uarts[i].istat.rxbuf_head = uarts[i].istat.rxbuf_tail = 0;
|
uarts[i].istat.txbuf_head = uarts[i].istat.txbuf_tail = 0;
|
uarts[i].istat.txbuf_head = uarts[i].istat.txbuf_tail = 0;
|
|
|
uarts[i].istat.break_set = 0;
|
uarts[i].istat.break_set = 0;
|
uarts[i].istat.timeout_count = 0;
|
uarts[i].istat.timeout_count = 0;
|
uarts[i].istat.thre_int = 1; /* FIFO is empty at start */
|
|
|
// For FIFO-mode only, THRE interrupt is set when both THR and FIFO are empty
|
|
uarts[i].istat.thre_int = (uarts[i].fifo_len == 16);
|
|
|
uarts[i].slowdown = UART_FGETC_SLOWDOWN;
|
uarts[i].slowdown = UART_FGETC_SLOWDOWN;
|
|
|
uarts[i].regs.lcr = UART_LCR_RESET;
|
uarts[i].regs.lcr = UART_LCR_RESET;
|
uarts[i].vapi.cur_break = uarts[i].vapi.cur_break_cnt = uarts[i].vapi.next_break = 0;
|
uarts[i].vapi.cur_break = uarts[i].vapi.cur_break_cnt = uarts[i].vapi.next_break = 0;
|
uarts[i].vapi.next_break_cnt = -1;
|
uarts[i].vapi.next_break_cnt = -1;
|
| Line 631... |
Line 630... |
continue;
|
continue;
|
PRINTF("\nUART%d visible registers at 0x%.8x:\n", i, config.uarts[i].baseaddr);
|
PRINTF("\nUART%d visible registers at 0x%.8x:\n", i, config.uarts[i].baseaddr);
|
PRINTF("RXBUF:");
|
PRINTF("RXBUF:");
|
for (j = uarts[i].istat.rxbuf_head; j != uarts[i].istat.rxbuf_tail; j = (j + 1) % uarts[i].fifo_len)
|
for (j = uarts[i].istat.rxbuf_head; j != uarts[i].istat.rxbuf_tail; j = (j + 1) % uarts[i].fifo_len)
|
PRINTF (" %.2x", uarts[i].regs.rxbuf[j]);
|
PRINTF (" %.2x", uarts[i].regs.rxbuf[j]);
|
PRINTF(" TXBUF: %.2x\n", uarts[i].regs.txbuf);
|
PRINTF("TXBUF: ");
|
|
for (j = uarts[i].istat.txbuf_head; j != uarts[i].istat.txbuf_tail; j = (j + 1) % uarts[i].fifo_len)
|
|
PRINTF (" %.2x", uarts[i].regs.txbuf[j]);
|
|
PRINTF("\n");
|
PRINTF("DLL : %.2x DLH : %.2x\n", uarts[i].regs.dll, uarts[i].regs.dlh);
|
PRINTF("DLL : %.2x DLH : %.2x\n", uarts[i].regs.dll, uarts[i].regs.dlh);
|
PRINTF("IER : %.2x IIR : %.2x\n", uarts[i].regs.ier, uarts[i].regs.iir);
|
PRINTF("IER : %.2x IIR : %.2x\n", uarts[i].regs.ier, uarts[i].regs.iir);
|
PRINTF("LCR : %.2x MCR : %.2x\n", uarts[i].regs.lcr, uarts[i].regs.mcr);
|
PRINTF("LCR : %.2x MCR : %.2x\n", uarts[i].regs.lcr, uarts[i].regs.mcr);
|
PRINTF("LSR : %.2x MSR : %.2x\n", uarts[i].regs.lsr, uarts[i].regs.msr);
|
PRINTF("LSR : %.2x MSR : %.2x\n", uarts[i].regs.lsr, uarts[i].regs.msr);
|
PRINTF("SCR : %.2x\n", uarts[i].regs.scr);
|
PRINTF("SCR : %.2x\n", uarts[i].regs.scr);
|
| Line 645... |
Line 647... |
|
|
PRINTF("\nInternal status (sim debug):\n");
|
PRINTF("\nInternal status (sim debug):\n");
|
PRINTF("char_clks: %d\n", uarts[i].char_clks);
|
PRINTF("char_clks: %d\n", uarts[i].char_clks);
|
PRINTF("rxser_clks: %d txser_clks: %d\n", uarts[i].istat.rxser_clks, uarts[i].istat.txser_clks);
|
PRINTF("rxser_clks: %d txser_clks: %d\n", uarts[i].istat.rxser_clks, uarts[i].istat.txser_clks);
|
PRINTF("rxser: %d txser: %d\n", uarts[i].istat.rxser_full, uarts[i].istat.txser_full);
|
PRINTF("rxser: %d txser: %d\n", uarts[i].istat.rxser_full, uarts[i].istat.txser_full);
|
PRINTF("rxbuf: %d txbuf: %d\n", uarts[i].istat.rxbuf_full, uarts[i].istat.txbuf_full);
|
PRINTF("rxbuf_full: %d txbuf_full: %d\n", uarts[i].istat.rxbuf_full, uarts[i].istat.txbuf_full);
|
PRINTF("Using IRQ%i\n", config.uarts[i].irq);
|
PRINTF("Using IRQ%i\n", config.uarts[i].irq);
|
if (config.uarts[i].vapi_id)
|
if (config.uarts[i].vapi_id)
|
PRINTF ("Connected to vapi ID=%x\n\n", config.uarts[i].vapi_id);
|
PRINTF ("Connected to vapi ID=%x\n\n", config.uarts[i].vapi_id);
|
/* TODO: replace by a channel_status
|
/* TODO: replace by a channel_status
|
else
|
else
|
