| Line 129... |
Line 129... |
ASSERT (r == ch); /* compare character */
|
ASSERT (r == ch); /* compare character */
|
}
|
}
|
|
|
/* Sends a char and checks for errors */
|
/* Sends a char and checks for errors */
|
|
|
|
void send_char_no_wait (int ch)
|
|
{
|
|
report (ch);
|
|
setreg (UART_THR, ch); /* send character */
|
|
}
|
|
|
void send_char (int ch)
|
void send_char (int ch)
|
{
|
{
|
report (ch);
|
report (ch);
|
while (!(getreg (UART_LSR) & LSR_TXFE));
|
while (!(getreg (UART_LSR) & LSR_TXFE));
|
NO_ERROR();
|
NO_ERROR();
|
| Line 164... |
Line 170... |
ASSERT(getreg (UART_RBR) == 0x00); //0
|
ASSERT(getreg (UART_RBR) == 0x00); //0
|
ASSERT(getreg (UART_IER) == 0x00); //1
|
ASSERT(getreg (UART_IER) == 0x00); //1
|
ASSERT(getreg (UART_IIR) == 0xc1); //2
|
ASSERT(getreg (UART_IIR) == 0xc1); //2
|
ASSERT(getreg (UART_LCR) == 0x03); //3
|
ASSERT(getreg (UART_LCR) == 0x03); //3
|
ASSERT(getreg (UART_MCR) == 0x00); //4
|
ASSERT(getreg (UART_MCR) == 0x00); //4
|
#if COMPLETE
|
|
ASSERT(getreg (UART_LSR) == 0x60); //5
|
ASSERT(getreg (UART_LSR) == 0x60); //5
|
ASSERT(getreg (UART_MSR) == 0x00); //6
|
ASSERT(getreg (UART_MSR) == 0x00); //6
|
#endif
|
|
ASSERT(getreg (UART_SCR) == 0x00); //7
|
ASSERT(getreg (UART_SCR) == 0x00); //7
|
|
|
setreg(UART_LCR, LCR_DIVL); //enable latches
|
setreg(UART_LCR, LCR_DIVL); //enable latches
|
ASSERT(getreg (UART_DLL) == 0x00); //0
|
ASSERT(getreg (UART_DLL) == 0x00); //0
|
ASSERT(getreg (UART_DLH) == 0x00); //1
|
ASSERT(getreg (UART_DLH) == 0x00); //1
|
setreg(UART_LCR, 0x00); //disable latches
|
setreg(UART_LCR, 0x00); //disable latches
|
}
|
}
|
|
setreg(UART_LCR, 0x00); //disable latches igor
|
|
setreg(UART_LCR, 0x00); //disable latches
|
|
setreg(UART_LCR, 0x00); //disable latches
|
|
setreg(UART_LCR, 0x00); //disable latches
|
|
setreg(UART_LCR, 0x00); //disable latches
|
|
|
#if COMPLETE
|
|
MARK();
|
MARK();
|
{ /* test if status registers are read only */
|
{ /* test if status registers are read only */
|
unsigned long tmp;
|
unsigned long tmp;
|
int i;
|
int i;
|
tmp = getreg (UART_LSR);
|
tmp = getreg (UART_LSR);
|
| Line 199... |
Line 207... |
for (i = 0; i < 9; i++) {
|
for (i = 0; i < 9; i++) {
|
setreg (UART_MSR, 1 << i);
|
setreg (UART_MSR, 1 << i);
|
ASSERT(getreg (UART_MSR) == tmp);
|
ASSERT(getreg (UART_MSR) == tmp);
|
}
|
}
|
}
|
}
|
#endif
|
|
|
|
MARK();
|
MARK();
|
{ /* test whether MCR is write only, be careful not to set the loopback bit */
|
{ /* test whether MCR is write only, be careful not to set the loopback bit */
|
#if COMPLETE
|
|
ASSERT(getreg (UART_MCR) == 0x00);
|
ASSERT(getreg (UART_MCR) == 0x00);
|
setreg (UART_MCR, 0x45);
|
setreg (UART_MCR, 0x45);
|
ASSERT(getreg (UART_MCR) == 0x00);
|
ASSERT(getreg (UART_MCR) == 0x00);
|
setreg (UART_MCR, 0xaa);
|
setreg (UART_MCR, 0xaa);
|
ASSERT(getreg (UART_MCR) == 0x00);
|
ASSERT(getreg (UART_MCR) == 0x00);
|
#endif
|
|
}
|
}
|
ASSERT (!(getreg (UART_LSR) & 0x1f));
|
ASSERT (!(getreg (UART_LSR) & 0x1f));
|
MARK();
|
MARK();
|
{ /* Test if Divisor latch byte holds the data */
|
{ /* Test if Divisor latch byte holds the data */
|
int i;
|
int i;
|
| Line 224... |
Line 229... |
setreg (UART_DLH, tmp >> 8);
|
setreg (UART_DLH, tmp >> 8);
|
setreg (UART_DLL, tmp & 0xff);
|
setreg (UART_DLL, tmp & 0xff);
|
ASSERT(getreg (UART_DLL) == (tmp & 0xff)); //0
|
ASSERT(getreg (UART_DLL) == (tmp & 0xff)); //0
|
ASSERT(getreg (UART_DLH) == (tmp >> 8)); //1
|
ASSERT(getreg (UART_DLH) == (tmp >> 8)); //1
|
}
|
}
|
|
setreg (UART_DLH, 0xa1); //igor
|
|
setreg (UART_DLH, 0xa1); //igor
|
|
setreg (UART_DLH, 0xa1); //igor
|
|
setreg (UART_DLH, 0xa1); //igor
|
|
setreg (UART_DLH, 0xa1); //igor
|
|
|
ASSERT (!(getreg (UART_LSR) & 0x1f));
|
ASSERT (!(getreg (UART_LSR) & 0x1f));
|
for (i = 0; i < 16; i++) {
|
for (i = 0; i < 16; i++) {
|
unsigned short tmp = 0xdead << i;
|
unsigned short tmp = 0xdead << i;
|
setreg (UART_DLL, tmp >> 8);
|
setreg (UART_DLL, tmp >> 8);
|
setreg (UART_DLH, tmp & 0xff);
|
setreg (UART_DLH, tmp & 0xff);
|
ASSERT(getreg (UART_DLL) == (tmp >> 8)); //1
|
ASSERT(getreg (UART_DLL) == (tmp >> 8)); //1
|
ASSERT(getreg (UART_DLH) == (tmp & 0xff)); //0
|
ASSERT(getreg (UART_DLH) == (tmp & 0xff)); //0
|
}
|
}
|
|
setreg (UART_DLH, 0xa2); //igor
|
|
setreg (UART_DLH, 0xa2); //igor
|
|
setreg (UART_DLH, 0xa2); //igor
|
|
setreg (UART_DLH, 0xa2); //igor
|
|
setreg (UART_DLH, 0xa2); //igor
|
|
|
setreg(UART_LCR, 0x00); //disable latches
|
setreg(UART_LCR, 0x00); //disable latches
|
ASSERT(getreg (UART_LCR) == 0x00);
|
ASSERT(getreg (UART_LCR) == 0x00);
|
ASSERT (!(getreg (UART_LSR) & 0x1f));
|
ASSERT (!(getreg (UART_LSR) & 0x1f));
|
}
|
}
|
MARK();
|
MARK();
|
| Line 246... |
Line 263... |
setreg (UART_LCR, tmp);
|
setreg (UART_LCR, tmp);
|
ASSERT(getreg (UART_LCR) == tmp);
|
ASSERT(getreg (UART_LCR) == tmp);
|
}
|
}
|
ASSERT (!(getreg (UART_LSR) & 0x1f));
|
ASSERT (!(getreg (UART_LSR) & 0x1f));
|
}
|
}
|
|
setreg (UART_LCR, 0xa3); //igor
|
|
setreg (UART_LCR, 0xa3); //igor
|
|
setreg (UART_LCR, 0xa3); //igor
|
|
setreg (UART_LCR, 0xa3); //igor
|
|
setreg (UART_LCR, 0xa3); //igor
|
|
|
MARK ();
|
MARK ();
|
|
|
{ /* SCR Test :))) */
|
{ /* SCR Test :))) */
|
int i;
|
int i;
|
setreg (UART_SCR, 0);
|
setreg (UART_SCR, 0);
|
| Line 260... |
Line 283... |
unsigned char tmp = 0xdead << i;
|
unsigned char tmp = 0xdead << i;
|
setreg (UART_SCR, tmp);
|
setreg (UART_SCR, tmp);
|
ASSERT (getreg (UART_SCR) == tmp);
|
ASSERT (getreg (UART_SCR) == tmp);
|
}
|
}
|
}
|
}
|
|
setreg (UART_SCR, 0xa5);//igor
|
|
setreg (UART_SCR, 0xa5);//igor
|
|
setreg (UART_SCR, 0xa5);//igor
|
|
setreg (UART_SCR, 0xa5);//igor
|
|
setreg (UART_SCR, 0xa5);//igor
|
|
|
MARK();
|
MARK();
|
/* Other registers will be tested later, if they function correctly,
|
/* Other registers will be tested later, if they function correctly,
|
since we cannot test them now, without destroying anything. */
|
since we cannot test them now, without destroying anything. */
|
}
|
}
|
|
|
| Line 335... |
Line 364... |
NO_ERROR();
|
NO_ERROR();
|
MARK();
|
MARK();
|
setreg (UART_LCR, 0x03 | LCR_BREAK); /* 8N1 */
|
setreg (UART_LCR, 0x03 | LCR_BREAK); /* 8N1 */
|
MARK();
|
MARK();
|
send_char ('b'); /* make sure it is recognised as a break */
|
send_char ('b'); /* make sure it is recognised as a break */
|
send_char ('b');
|
|
send_char ('b');
|
|
send_char ('b');
|
|
MARK();
|
MARK();
|
recv_char ('*');
|
recv_char ('*');
|
setreg (UART_LCR, 0x03); /* deleting break bit, 8N1 */
|
setreg (UART_LCR, 0x03); /* deleting break bit, 8N1 */
|
MARK();
|
MARK();
|
|
|
| Line 488... |
Line 514... |
setreg (UART_DLH, 6 >> 8); /* Set relatively slow speed, so we can hanlde interrupts properly */
|
setreg (UART_DLH, 6 >> 8); /* Set relatively slow speed, so we can hanlde interrupts properly */
|
setreg (UART_DLL, 6 & 0xff);
|
setreg (UART_DLL, 6 & 0xff);
|
setreg (UART_LCR, 0x03); /* 8N1 @ 6 */
|
setreg (UART_LCR, 0x03); /* 8N1 @ 6 */
|
|
|
ASSERT (int_cnt == 0); /* We should not have got any interrupts before this test */
|
ASSERT (int_cnt == 0); /* We should not have got any interrupts before this test */
|
setreg (UART_IER, 0x07); /* Enable interrupts: line status, THR empty, data ready */
|
|
setreg (UART_FCR, 0x01); /* Set trigger level = 1 char, fifo should not be reset */
|
setreg (UART_FCR, 0x01); /* Set trigger level = 1 char, fifo should not be reset */
|
MARK();
|
setreg (UART_IER, 0x07); /* Enable interrupts: line status, THR empty, data ready */
|
|
|
#if 0
|
|
while (!int_cnt); /* Clear previous THR interrupt */
|
while (!int_cnt); /* Clear previous THR interrupt */
|
ASSERT (--int_cnt == 0);
|
ASSERT (--int_cnt == 0);
|
ASSERT (int_iir == 0xc2);
|
ASSERT (int_iir == 0xc2);
|
ASSERT ((int_lsr & 0xbe) == 0x20);
|
ASSERT ((int_lsr & 0xbe) == 0x20);
|
MARK();
|
MARK();
|
#endif
|
|
|
|
/* I am configured - start interrupt test */
|
/* I am configured - start interrupt test */
|
send_char ('I');
|
send_char ('I');
|
while (!int_cnt); /* Wait for THR to be empty */
|
while (!int_cnt); /* Wait for THR to be empty */
|
ASSERT (--int_cnt == 0);
|
ASSERT (--int_cnt == 0);
|
| Line 699... |
Line 722... |
send_char ('!');
|
send_char ('!');
|
recv_char ('!');
|
recv_char ('!');
|
MARK ();
|
MARK ();
|
|
|
/* FCR2 - reset tx FIFO */
|
/* FCR2 - reset tx FIFO */
|
send_char ('1');
|
send_char_no_wait ('1');
|
send_char ('2');
|
send_char_no_wait ('2');
|
|
// send_char ('1');
|
|
// send_char ('2');
|
setreg (UART_FCR, 4); /* Should clear '2' from fifo, but '1' should be sent OK */
|
setreg (UART_FCR, 4); /* Should clear '2' from fifo, but '1' should be sent OK */
|
ASSERT (getreg (UART_LSR) == 0x00); /* we should still be sending '1' */
|
ASSERT (getreg (UART_LSR) == 0x00); /* we should still be sending '1' */
|
NO_ERROR();
|
NO_ERROR();
|
send_char ('*');
|
send_char ('*');
|
recv_char ('*');
|
recv_char ('*');
|
| Line 774... |
Line 799... |
|
|
/* Enable interrupts */
|
/* Enable interrupts */
|
mtspr (SPR_SR, mfspr(SPR_SR) | SPR_SR_EXR | SPR_SR_EIR);
|
mtspr (SPR_SR, mfspr(SPR_SR) | SPR_SR_EXR | SPR_SR_EIR);
|
mtspr (SPR_PICMR, mfspr(SPR_PICMR) | (0x00000001L << UART_INT_LINE));
|
mtspr (SPR_PICMR, mfspr(SPR_PICMR) | (0x00000001L << UART_INT_LINE));
|
|
|
register_test ();
|
// register_test ();
|
init_8n1 ();
|
init_8n1 ();
|
|
// control_register_test ();
|
// send_recv_test ();
|
// send_recv_test ();
|
// break_test ();
|
// break_test ();
|
different_modes_test ();
|
// different_modes_test ();
|
interrupt_test ();
|
interrupt_test ();
|
control_register_test ();
|
// line_error_test ();
|
line_error_test ();
|
|
|
|
/* loopback_test ();
|
/* loopback_test ();
|
modem_test ();
|
modem_test ();
|
modem_error_test ();*/
|
modem_error_test ();*/
|
recv_char ('@');
|
recv_char ('@');
|
