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[/] [or1k/] [tags/] [stable_0_2_0/] [or1ksim/] [cache/] [icache_model.c] - Diff between revs 1432 and 1486

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Rev 1432 Rev 1486
Line 78... Line 78...
    - set 'lru' with config.ic.ustates - 1 and decrement 'lru' of other
    - set 'lru' with config.ic.ustates - 1 and decrement 'lru' of other
      ways unless they have reached 0
      ways unless they have reached 0
    - refill cache line
    - refill cache line
*/
*/
 
 
uint32_t ic_simulate_fetch(oraddr_t fetchaddr)
uint32_t ic_simulate_fetch(oraddr_t fetchaddr, oraddr_t virt_addr)
{
{
  int set, way = -1;
  int set, way = -1;
  int i;
  int i;
  oraddr_t tagaddr;
  oraddr_t tagaddr;
  uint32_t tmp;
  uint32_t tmp;
 
 
  /* ICache simulation enabled/disabled. */
  /* ICache simulation enabled/disabled. */
  if ((!testsprbits(SPR_UPR, SPR_UPR_ICP)) || (!testsprbits(SPR_SR, SPR_SR_ICE)) || insn_ci) {
  if ((!testsprbits(SPR_UPR, SPR_UPR_ICP)) || (!testsprbits(SPR_SR, SPR_SR_ICE)) || insn_ci) {
    tmp = evalsim_mem32(fetchaddr);
    tmp = evalsim_mem32(fetchaddr, virt_addr);
    if(!cur_area) {
    if (cur_area && cur_area->log)
      printf("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR")\n",
 
             fetchaddr);
 
      except_handle(EXCEPT_BUSERR, cur_vadd);
 
      return 0;
 
    } else if (cur_area->log)
 
      fprintf (cur_area->log, "[%"PRIxADDR"] -> read %08"PRIx32"\n", fetchaddr,
      fprintf (cur_area->log, "[%"PRIxADDR"] -> read %08"PRIx32"\n", fetchaddr,
               tmp);
               tmp);
    return tmp;
    return tmp;
  }
  }
 
 
Line 134... Line 129...
      }
      }
    }
    }
 
 
    for (i = 0; i < (config.ic.blocksize); i += 4) {
    for (i = 0; i < (config.ic.blocksize); i += 4) {
      tmp = ic[set].way[minway].line[((fetchaddr + i) & (config.ic.blocksize - 1)) >> 2] =
      tmp = ic[set].way[minway].line[((fetchaddr + i) & (config.ic.blocksize - 1)) >> 2] =
        evalsim_mem32((fetchaddr & ~(config.ic.blocksize - 1)) + ((fetchaddr + i) & (config.ic.blocksize - 1)));
        /* FIXME: What is the virtual address meant to be? (ie. What happens if
 
         * we read out of memory while refilling a cache line?) */
 
        evalsim_mem32((fetchaddr & ~(config.ic.blocksize - 1)) + ((fetchaddr + i) & (config.ic.blocksize - 1)), 0);
      if(!cur_area) {
      if(!cur_area) {
        ic[set].way[minway].tagaddr = -1;
        ic[set].way[minway].tagaddr = -1;
        ic[set].way[minway].lru = 0;
        ic[set].way[minway].lru = 0;
        printf("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR")\n",
 
               fetchaddr);
 
        except_handle(EXCEPT_BUSERR, cur_vadd);
 
        return 0;
        return 0;
      } else if (cur_area->log)
      } else if (cur_area->log)
        fprintf (cur_area->log, "[%"PRIxADDR"] -> read %08"PRIx32"\n",
        fprintf (cur_area->log, "[%"PRIxADDR"] -> read %08"PRIx32"\n",
                 fetchaddr, tmp);
                 fetchaddr, tmp);
    }
    }

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