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[/] [or1k/] [tags/] [stable_0_2_0/] [or1ksim/] [cpu/] [or1k/] [sprs.c] - Diff between revs 1532 and 1540

Rev 1532	Rev 1540
Line 62...	Line 62...
`switch (regno) {`	`switch (regno) {`
`case SPR_TTCR:`	`case SPR_TTCR:`
`spr_write_ttcr (value);`	`spr_write_ttcr (value);`
`break;`	`break;`
`case SPR_TTMR:`	`case SPR_TTMR:`
`spr_write_ttmr (value);`	`spr_write_ttmr (prev_val);`
`break;`	`break;`
`/* Data cache simulateing stuff */`	`/* Data cache simulateing stuff */`
`case SPR_DCBPR:`	`case SPR_DCBPR:`
`/* FIXME: This is not correct. The arch. manual states: "Memory accesses`	`/* FIXME: This is not correct. The arch. manual states: "Memory accesses`
`* are not recorded (Unlike load or store instructions) and cannot invoke`	`* are not recorded (Unlike load or store instructions) and cannot invoke`