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[/] [or1k/] [tags/] [stable_0_2_0/] [or1ksim/] [cpu/] [or32/] [insnset.c] - Diff between revs 1513 and 1537

Rev 1513	Rev 1537
Line 432...	Line 432...
`}`	`}`
`INSTRUCTION (l_mtspr) {`	`INSTRUCTION (l_mtspr) {`
`uint16_t regno = PARAM0 + PARAM2;`	`uint16_t regno = PARAM0 + PARAM2;`
`uorreg_t value = PARAM1;`	`uorreg_t value = PARAM1;`

`if (runtime.sim.fspr_log) {`
`fprintf(runtime.sim.fspr_log, "Write to SPR : [%08"PRIx16"] <- [%08"PRIx32"]\n", regno, value);`
`}`

`if (cpu_state.sprs[SPR_SR] & SPR_SR_SM)`	`if (cpu_state.sprs[SPR_SR] & SPR_SR_SM)`
`mtspr(regno, value);`	`mtspr(regno, value);`
`else {`	`else {`
`PRINTF("WARNING: trying to write SPR while SR[SUPV] is cleared.\n");`	`PRINTF("WARNING: trying to write SPR while SR[SUPV] is cleared.\n");`
`sim_done();`	`sim_done();`
Line 447...	Line 443...
`}`	`}`
`INSTRUCTION (l_mfspr) {`	`INSTRUCTION (l_mfspr) {`
`uint16_t regno = PARAM1 + PARAM2;`	`uint16_t regno = PARAM1 + PARAM2;`
`uorreg_t value = mfspr(regno);`	`uorreg_t value = mfspr(regno);`

`if (runtime.sim.fspr_log) {`
`fprintf(runtime.sim.fspr_log, "Read from SPR : [%08"PRIx16"] -> [%08"PRIx32"]\n", regno, value);`
`}`

`if (cpu_state.sprs[SPR_SR] & SPR_SR_SM)`	`if (cpu_state.sprs[SPR_SR] & SPR_SR_SM)`
`SET_PARAM0(value);`	`SET_PARAM0(value);`
`else {`	`else {`
`SET_PARAM0(0);`	`SET_PARAM0(0);`
`PRINTF("WARNING: trying to read SPR while SR[SUPV] is cleared.\n");`	`PRINTF("WARNING: trying to read SPR while SR[SUPV] is cleared.\n");`