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[/] [or1k/] [tags/] [stable_0_2_0/] [or1ksim/] [mmu/] [immu.c] - Diff between revs 1506 and 1508

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Rev 1506 Rev 1508
Line 62... Line 62...
  tagaddr = (virtaddr / config.immu.pagesize) / config.immu.nsets;
  tagaddr = (virtaddr / config.immu.pagesize) / config.immu.nsets;
  vpn = virtaddr / (config.immu.pagesize * config.immu.nsets);
  vpn = virtaddr / (config.immu.pagesize * config.immu.nsets);
 
 
  /* Scan all ways and try to find a matching way. */
  /* Scan all ways and try to find a matching way. */
  for (i = 0; i < config.immu.nways; i++)
  for (i = 0; i < config.immu.nways; i++)
    if (((mfspr(SPR_ITLBMR_BASE(i) + set) / (config.immu.pagesize * config.immu.nsets)) == vpn) &&
    if (((cpu_state.sprs[SPR_ITLBMR_BASE(i) + set] / (config.immu.pagesize * config.immu.nsets)) == vpn) &&
        (cpu_state.sprs[SPR_ITLBMR_BASE(i) + set] & SPR_ITLBMR_V))
        (cpu_state.sprs[SPR_ITLBMR_BASE(i) + set] & SPR_ITLBMR_V))
      way = i;
      way = i;
 
 
  /* Did we find our tlb entry? */
  /* Did we find our tlb entry? */
  if (way >= 0) { /* Yes, we did. */
  if (way >= 0) { /* Yes, we did. */
Line 83... Line 83...
    }
    }
    cpu_state.sprs[SPR_ITLBMR_BASE(way) + set] &= ~SPR_ITLBMR_LRU;
    cpu_state.sprs[SPR_ITLBMR_BASE(way) + set] &= ~SPR_ITLBMR_LRU;
    cpu_state.sprs[SPR_ITLBMR_BASE(way) + set] |= (config.immu.nsets - 1) << 6;
    cpu_state.sprs[SPR_ITLBMR_BASE(way) + set] |= (config.immu.nsets - 1) << 6;
 
 
    /* Check if page is cache inhibited */
    /* Check if page is cache inhibited */
    insn_ci = (mfspr(SPR_ITLBTR_BASE(way) + set) & SPR_ITLBTR_CI) == SPR_ITLBTR_CI;
    insn_ci = (cpu_state.sprs[SPR_ITLBTR_BASE(way) + set] & SPR_ITLBTR_CI) == SPR_ITLBTR_CI;
 
 
    runtime.sim.mem_cycles += config.immu.hitdelay;
    runtime.sim.mem_cycles += config.immu.hitdelay;
 
 
    /* Test for page fault */
    /* Test for page fault */
    if (mfspr (SPR_SR) & SPR_SR_SM) {
    if (cpu_state.sprs[SPR_SR] & SPR_SR_SM) {
      if (!(mfspr (SPR_ITLBTR_BASE(way) + set) & SPR_ITLBTR_SXE))
      if (!(cpu_state.sprs[SPR_ITLBTR_BASE(way) + set] & SPR_ITLBTR_SXE))
        except_handle(EXCEPT_IPF, virtaddr);
        except_handle(EXCEPT_IPF, virtaddr);
    } else {
    } else {
      if (!(mfspr (SPR_ITLBTR_BASE(way) + set) & SPR_ITLBTR_UXE))
      if (!(cpu_state.sprs[SPR_ITLBTR_BASE(way) + set] & SPR_ITLBTR_UXE))
        except_handle(EXCEPT_IPF, virtaddr);
        except_handle(EXCEPT_IPF, virtaddr);
    }
    }
 
 
    ppn = mfspr(SPR_ITLBTR_BASE(way) + set) / config.immu.pagesize;
    ppn = cpu_state.sprs[SPR_ITLBTR_BASE(way) + set] / config.immu.pagesize;
    return (ppn * config.immu.pagesize) + (virtaddr % config.immu.pagesize);
    return (ppn * config.immu.pagesize) + (virtaddr % config.immu.pagesize);
  }
  }
  else {  /* No, we didn't. */
  else {  /* No, we didn't. */
    immu_stats.fetch_tlbmiss++;
    immu_stats.fetch_tlbmiss++;
#if 0
#if 0
Line 163... Line 163...
  tagaddr = (virtaddr / config.immu.pagesize) / config.immu.nsets;
  tagaddr = (virtaddr / config.immu.pagesize) / config.immu.nsets;
  vpn = virtaddr / (config.immu.pagesize * config.immu.nsets);
  vpn = virtaddr / (config.immu.pagesize * config.immu.nsets);
 
 
  /* Scan all ways and try to find a matching way. */
  /* Scan all ways and try to find a matching way. */
  for (i = 0; i < config.immu.nways; i++)
  for (i = 0; i < config.immu.nways; i++)
    if (((mfspr(SPR_ITLBMR_BASE(i) + set) / (config.immu.pagesize * config.immu.nsets)) == vpn) &&
    if (((cpu_state.sprs[SPR_ITLBMR_BASE(i) + set] / (config.immu.pagesize * config.immu.nsets)) == vpn) &&
        (cpu_state.sprs[SPR_ITLBMR_BASE(i) + set] & SPR_ITLBMR_V))
        (cpu_state.sprs[SPR_ITLBMR_BASE(i) + set] & SPR_ITLBMR_V))
      way = i;
      way = i;
 
 
  /* Did we find our tlb entry? */
  /* Did we find our tlb entry? */
  if (way >= 0) { /* Yes, we did. */
  if (way >= 0) { /* Yes, we did. */
 
 
    /* Test for page fault */
    /* Test for page fault */
    if (mfspr (SPR_SR) & SPR_SR_SM) {
    if (cpu_state.sprs[SPR_SR] & SPR_SR_SM) {
      if (!(mfspr (SPR_ITLBTR_BASE(way) + set) & SPR_ITLBTR_SXE)) {
      if (!(cpu_state.sprs[SPR_ITLBTR_BASE(way) + set] & SPR_ITLBTR_SXE)) {
        /* no luck, giving up */
        /* no luck, giving up */
        return(0);
        return(0);
      }
      }
    } else {
    } else {
      if (!(mfspr (SPR_ITLBTR_BASE(way) + set) & SPR_ITLBTR_UXE)) {
      if (!(cpu_state.sprs[SPR_ITLBTR_BASE(way) + set] & SPR_ITLBTR_UXE)) {
        /* no luck, giving up */
        /* no luck, giving up */
        return(0);
        return(0);
      }
      }
    }
    }
 
 
    ppn = mfspr(SPR_ITLBTR_BASE(way) + set) / config.immu.pagesize;
    ppn = cpu_state.sprs[SPR_ITLBTR_BASE(way) + set] / config.immu.pagesize;
    return (ppn * config.immu.pagesize) + (virtaddr % config.immu.pagesize);
    return (ppn * config.immu.pagesize) + (virtaddr % config.immu.pagesize);
  }
  }
  else {
  else {
    return(0);
    return(0);
  }
  }

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