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Line 27... |
#include <inttypes.h>
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#include <inttypes.h>
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#endif
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#endif
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#include "port.h"
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#include "port.h"
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#include "arch.h"
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#include "arch.h"
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/* get a prototype for 'register_memoryarea()', and 'adjust_rw_delay()' */
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/* get a prototype for 'reg_mem_area()', and 'adjust_rw_delay()' */
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#include "abstract.h"
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#include "abstract.h"
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#include "sim-config.h"
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#include "sim-config.h"
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#include "sched.h"
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#include "sched.h"
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/* all user defineable settings are in 'atahost_define.h' */
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/* all user defineable settings are in 'atahost_define.h' */
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Line 53... |
ata->regs.dtr0 = (DMA_MODE0_TEOC << ATA_TEOC) | (DMA_MODE0_TD << ATA_TD) | (DMA_MODE0_TM << ATA_TM);
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ata->regs.dtr0 = (DMA_MODE0_TEOC << ATA_TEOC) | (DMA_MODE0_TD << ATA_TD) | (DMA_MODE0_TM << ATA_TM);
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ata->regs.dtr1 = (DMA_MODE0_TEOC << ATA_TEOC) | (DMA_MODE0_TD << ATA_TD) | (DMA_MODE0_TM << ATA_TM);
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ata->regs.dtr1 = (DMA_MODE0_TEOC << ATA_TEOC) | (DMA_MODE0_TD << ATA_TD) | (DMA_MODE0_TM << ATA_TM);
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ata->regs.txb = 0;
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ata->regs.txb = 0;
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// inform simulator about new read/write delay timings
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// inform simulator about new read/write delay timings
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adjust_rw_delay( ata->baseaddr, ata_pio_delay(ata->regs.pctr), ata_pio_delay(ata->regs.pctr) );
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adjust_rw_delay( ata->mem, ata_pio_delay(ata->regs.pctr), ata_pio_delay(ata->regs.pctr) );
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/* the reset bit in the control register 'ctrl' is set, reset connect ata-devices */
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/* the reset bit in the control register 'ctrl' is set, reset connect ata-devices */
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ata_devices_hw_reset(&ata->devices, 1);
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ata_devices_hw_reset(&ata->devices, 1);
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}
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}
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/* ========================================================================= */
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/* ========================================================================= */
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Line 68... |
*/
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*/
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uint32_t ata_read32( oraddr_t addr, void *dat )
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uint32_t ata_read32( oraddr_t addr, void *dat )
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{
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{
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ata_host *ata = dat;
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ata_host *ata = dat;
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addr -= ata->baseaddr;
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/* determine if ata_host or ata_device addressed */
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/* determine if ata_host or ata_device addressed */
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if (is_ata_hostadr(addr))
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if (is_ata_hostadr(addr))
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{
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{
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// Accesses to internal register take 2cycles
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// Accesses to internal register take 2cycles
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adjust_rw_delay( ata->baseaddr, 2, 2 );
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adjust_rw_delay( ata->mem, 2, 2 );
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switch( addr ) {
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switch( addr ) {
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case ATA_CTRL :
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case ATA_CTRL :
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return ata -> regs.ctrl;
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return ata -> regs.ctrl;
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// make sure simulator uses correct read/write delay timings
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// make sure simulator uses correct read/write delay timings
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#if (DEV_ID > 1)
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#if (DEV_ID > 1)
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if ( (addr & 0x7f) == ATA_DR)
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if ( (addr & 0x7f) == ATA_DR)
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{
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{
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if (ata->devices.dev)
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if (ata->devices.dev)
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adjust_rw_delay( ata->baseaddr, ata_pio_delay(ata->regs.ftcr1), ata_pio_delay(ata->regs.ftcr1) );
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adjust_rw_delay( ata->mem, ata_pio_delay(ata->regs.ftcr1), ata_pio_delay(ata->regs.ftcr1) );
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else
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else
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adjust_rw_delay( ata->baseaddr, ata_pio_delay(ata->regs.ftcr0), ata_pio_delay(ata->regs.ftcr0) );
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adjust_rw_delay( ata->mem, ata_pio_delay(ata->regs.ftcr0), ata_pio_delay(ata->regs.ftcr0) );
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}
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}
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else
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else
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#endif
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#endif
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adjust_rw_delay( ata->baseaddr, ata_pio_delay(ata->regs.pctr), ata_pio_delay(ata->regs.pctr) );
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adjust_rw_delay( ata->mem, ata_pio_delay(ata->regs.pctr), ata_pio_delay(ata->regs.pctr) );
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return ata_devices_read(&ata->devices, addr & 0x7f);
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return ata_devices_read(&ata->devices, addr & 0x7f);
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}
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}
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}
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}
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/* ========================================================================= */
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/* ========================================================================= */
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Line 137... |
*/
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*/
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void ata_write32( oraddr_t addr, uint32_t value, void *dat )
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void ata_write32( oraddr_t addr, uint32_t value, void *dat )
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{
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{
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ata_host *ata = dat;
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ata_host *ata = dat;
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addr -= ata->baseaddr;
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/* determine if ata_host or ata_device addressed */
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/* determine if ata_host or ata_device addressed */
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if (is_ata_hostadr(addr))
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if (is_ata_hostadr(addr))
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{
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{
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// Accesses to internal register take 2cycles
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// Accesses to internal register take 2cycles
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adjust_rw_delay( ata->baseaddr, 2, 2 );
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adjust_rw_delay( ata->mem, 2, 2 );
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switch( addr ) {
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switch( addr ) {
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case ATA_CTRL :
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case ATA_CTRL :
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ata -> regs.ctrl = value;
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ata -> regs.ctrl = value;
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Line 203... |
// make sure simulator uses correct read/write delay timings
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// make sure simulator uses correct read/write delay timings
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#if (DEV_ID > 1)
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#if (DEV_ID > 1)
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if ( (addr & 0x7f) == ATA_DR)
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if ( (addr & 0x7f) == ATA_DR)
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{
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{
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if (ata->devices.dev)
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if (ata->devices.dev)
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adjust_rw_delay( ata->baseaddr, ata_pio_delay(ata->regs.ftcr1), ata_pio_delay(ata->regs.ftcr1) );
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adjust_rw_delay( ata->mem, ata_pio_delay(ata->regs.ftcr1), ata_pio_delay(ata->regs.ftcr1) );
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else
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else
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adjust_rw_delay( ata->baseaddr, ata_pio_delay(ata->regs.ftcr0), ata_pio_delay(ata->regs.ftcr0) );
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adjust_rw_delay( ata->mem, ata_pio_delay(ata->regs.ftcr0), ata_pio_delay(ata->regs.ftcr0) );
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}
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}
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else
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else
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#endif
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#endif
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adjust_rw_delay( ata->baseaddr, ata_pio_delay(ata->regs.pctr), ata_pio_delay(ata->regs.pctr) );
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adjust_rw_delay( ata->mem, ata_pio_delay(ata->regs.pctr), ata_pio_delay(ata->regs.pctr) );
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ata_devices_write(&ata->devices, addr & 0x7f, value);
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ata_devices_write(&ata->devices, addr & 0x7f, value);
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}
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}
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}
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}
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/* ========================================================================= */
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/* ========================================================================= */
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Line 334... |
}
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}
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void ata_sec_end(void *dat)
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void ata_sec_end(void *dat)
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{
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{
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ata_host *ata = dat;
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ata_host *ata = dat;
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struct mem_ops ops;
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if(!ata->enabled) {
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if(!ata->enabled) {
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free(dat);
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free(dat);
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return;
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return;
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}
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}
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/* Connect ata_devices. */
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/* Connect ata_devices. */
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ata_devices_init(&ata->devices);
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ata_devices_init(&ata->devices);
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register_memoryarea(ata->baseaddr, ATA_ADDR_SPACE, 4, 0, ata_read32, ata_write32, dat);
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memset(&ops, 0, sizeof(struct mem_ops));
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ops.readfunc32 = ata_read32;
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ops.read_dat32 = dat;
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ops.writefunc32 = ata_write32;
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ops.write_dat32 = dat;
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/* Delays will be readjusted later */
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ops.delayr = 2;
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ops.delayw = 2;
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ata->mem = reg_mem_area(ata->baseaddr, ATA_ADDR_SPACE, 0, &ops);
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reg_sim_reset(ata_reset, dat);
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reg_sim_reset(ata_reset, dat);
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reg_sim_stat(ata_status, dat);
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reg_sim_stat(ata_status, dat);
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}
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}
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