URL
https://opencores.org/ocsvn/or1k/or1k/trunk
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 631 |
Rev 638 |
| Line 75... |
Line 75... |
int i;
|
int i;
|
unsigned long tagaddr;
|
unsigned long tagaddr;
|
extern int mem_cycles;
|
extern int mem_cycles;
|
|
|
/* ICache simulation enabled/disabled. */
|
/* ICache simulation enabled/disabled. */
|
if ((!testsprbits(SPR_UPR, SPR_UPR_ICP)) || (!testsprbits(SPR_SR, SPR_SR_ICE)))
|
if ((!testsprbits(SPR_UPR, SPR_UPR_ICP)) || (!testsprbits(SPR_SR, SPR_SR_ICE)) || insn_ci)
|
return evalsim_mem32(fetchaddr);
|
return evalsim_mem32(fetchaddr);
|
|
|
/* Which set to check out? */
|
/* Which set to check out? */
|
set = (fetchaddr / config.ic.blocksize) % config.ic.nsets;
|
set = (fetchaddr / config.ic.blocksize) % config.ic.nsets;
|
tagaddr = (fetchaddr / config.ic.blocksize) / config.ic.nsets;
|
tagaddr = (fetchaddr / config.ic.blocksize) / config.ic.nsets;
|
| Line 111... |
Line 111... |
minway = i;
|
minway = i;
|
|
|
for (i = 0; i < (config.ic.blocksize); i += 4) {
|
for (i = 0; i < (config.ic.blocksize); i += 4) {
|
ic[set].way[minway].line[((fetchaddr + i) & (config.ic.blocksize - 1)) >> 2] =
|
ic[set].way[minway].line[((fetchaddr + i) & (config.ic.blocksize - 1)) >> 2] =
|
evalsim_mem32((fetchaddr & ~(config.ic.blocksize - 1)) + ((fetchaddr + i) & (config.ic.blocksize - 1)));
|
evalsim_mem32((fetchaddr & ~(config.ic.blocksize - 1)) + ((fetchaddr + i) & (config.ic.blocksize - 1)));
|
if(!cur_area)
|
if(!cur_area) {
|
|
ic[set].way[minway].tagaddr = -1;
|
|
ic[set].way[minway].lru = 0;
|
return 0;
|
return 0;
|
}
|
}
|
|
}
|
|
|
ic[set].way[minway].tagaddr = tagaddr;
|
ic[set].way[minway].tagaddr = tagaddr;
|
for (i = 0; i < config.ic.nways; i++)
|
for (i = 0; i < config.ic.nways; i++)
|
if (ic[set].way[i].lru)
|
if (ic[set].way[i].lru)
|
ic[set].way[i].lru--;
|
ic[set].way[i].lru--;
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.