| Line 78... |
Line 78... |
except, except_name(except), pcprev, ea, cpu_state.pc, pcnext,
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except, except_name(except), pcprev, ea, cpu_state.pc, pcnext,
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cpu_state.pc_delay, runtime.sim.cycles, runtime.cpu.instructions);
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cpu_state.pc_delay, runtime.sim.cycles, runtime.cpu.instructions);
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pcnext = except + (testsprbits (SPR_SR, SPR_SR_EPH) ? 0xf0000000 : 0x00000000);
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pcnext = except + (testsprbits (SPR_SR, SPR_SR_EPH) ? 0xf0000000 : 0x00000000);
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cpu_state.sprs[SPR_EEAR_BASE] = ea;
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cpu_state.sprs[SPR_ESR_BASE] = cpu_state.sprs[SPR_SR];
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cpu_state.sprs[SPR_SR] &= ~SPR_SR_OVE; /* Disable overflow flag exception. */
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cpu_state.sprs[SPR_SR] |= SPR_SR_SM; /* SUPV mode */
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cpu_state.sprs[SPR_SR] &= ~(SPR_SR_IEE | SPR_SR_TEE); /* Disable interrupts. */
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/* Address translation is always disabled when starting exception. */
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cpu_state.sprs[SPR_SR] &= ~SPR_SR_DME;
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cpu_state.sprs[SPR_SR] &= ~SPR_SR_IME;
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switch(except) {
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switch(except) {
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/* EPCR is irrelevent */
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/* EPCR is irrelevent */
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case EXCEPT_RESET:
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case EXCEPT_RESET:
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break;
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break;
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/* EPCR is loaded with address of instruction that caused the exception */
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/* EPCR is loaded with address of instruction that caused the exception */
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| Line 112... |
Line 124... |
cpu_state.pc = pcnext;
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cpu_state.pc = pcnext;
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pcnext += 4;
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pcnext += 4;
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break;
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break;
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}
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}
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mtspr(SPR_EEAR_BASE, ea);
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mtspr(SPR_ESR_BASE, mfspr(SPR_SR));
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/* Address translation is always disabled when starting exception. */
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mtspr(SPR_SR, mfspr(SPR_SR) & ~(SPR_SR_DME));
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mtspr(SPR_SR, mfspr(SPR_SR) & ~(SPR_SR_IME));
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mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_OVE); /* Disable overflow flag exception. */
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mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_SM); /* SUPV mode */
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mtspr(SPR_SR, mfspr(SPR_SR) & ~(SPR_SR_IEE | SPR_SR_TEE)); /* Disable interrupts. */
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cpu_state.delay_insn = 0;
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cpu_state.delay_insn = 0;
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}
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}
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No newline at end of file
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No newline at end of file
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