URL https://opencores.org/ocsvn/or1k/or1k/trunk

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[/] [or1k/] [tags/] [stable_0_2_0_rc1/] [or1ksim/] [cuc/] [insn.h] - Diff between revs 883 and 897

Rev 883	Rev 897
Line 60...	Line 60...
`#define II_IS_LOAD(x) ((x) == II_LB \|\| (x) == II_LH \|\| (x) == II_LW)`	`#define II_IS_LOAD(x) ((x) == II_LB \|\| (x) == II_LH \|\| (x) == II_LW)`
`#define II_MEM_WIDTH(x) (((x) == II_LB \|\| (x) == II_SB) ? 1 :\`	`#define II_MEM_WIDTH(x) (((x) == II_LB \|\| (x) == II_SB) ? 1 :\`
`((x) == II_LH \|\| (x) == II_SH) ? 2 :\`	`((x) == II_LH \|\| (x) == II_SH) ? 2 :\`
`((x) == II_LW \|\| (x) == II_SW) ? 4 : -1)`	`((x) == II_LW \|\| (x) == II_SW) ? 4 : -1)`

`/* Clock speed in ns */`
`extern double cycle_duration;`

`/* List of known instructions and their rtl representation */`	`/* List of known instructions and their rtl representation */`
`typedef struct {`	`typedef struct {`
`char *name;`	`char *name;`
`int comutative;`	`int comutative;`
`char *rtl;`	`char *rtl;`
Line 104...	Line 101...
`const char cuc_insn_name (cuc_insn ii);`	`const char cuc_insn_name (cuc_insn ii);`

`/* Loads in the specified timings table */`	`/* Loads in the specified timings table */`
`void load_timing_table (char *filename);`	`void load_timing_table (char *filename);`

	`/* Displays shared instructions */`
	`void print_shared (cuc_func rf, cuc_shared_item shared, int nshared);`

`#endif /* _DF_INSN_ */`	`#endif /* _DF_INSN_ */`


`No newline at end of file`	`No newline at end of file`