| Line 237... |
Line 237... |
* This does the actual "DMA" operation.
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* This does the actual "DMA" operation.
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* One chunk is transferred per clock.
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* One chunk is transferred per clock.
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*/
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*/
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void dma_channel_clock( void *dat )
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void dma_channel_clock( void *dat )
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{
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{
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int breakpoint = 0;
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struct dma_channel *channel = dat;
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struct dma_channel *channel = dat;
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|
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/* Do we need to abort? */
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/* Do we need to abort? */
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if ( TEST_FLAG( channel->regs.csr, DMA_CH_CSR, STOP ) ) {
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if ( TEST_FLAG( channel->regs.csr, DMA_CH_CSR, STOP ) ) {
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debug( 3, "DMA: STOP requested\n" );
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debug( 3, "DMA: STOP requested\n" );
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| Line 290... |
Line 289... |
return;
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return;
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}
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}
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}
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}
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|
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/* Transfer one word */
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/* Transfer one word */
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set_direct32( channel->destination, eval_direct32( channel->source,
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set_direct32( channel->destination, eval_direct32( channel->source, 0, 0 ),
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&breakpoint, 0, 0 ),
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0, 0 );
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&breakpoint, 0, 0 );
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|
|
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/* Advance the source and destionation pointers */
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/* Advance the source and destionation pointers */
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masked_increase( &(channel->source), channel->source_mask );
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masked_increase( &(channel->source), channel->source_mask );
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masked_increase( &(channel->destination), channel->destination_mask );
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masked_increase( &(channel->destination), channel->destination_mask );
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++ channel->words_transferred;
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++ channel->words_transferred;
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| Line 323... |
Line 321... |
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|
|
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/* Copy relevant valued from linked list descriptor to channel registers */
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/* Copy relevant valued from linked list descriptor to channel registers */
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void dma_load_descriptor( struct dma_channel *channel )
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void dma_load_descriptor( struct dma_channel *channel )
|
{
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{
|
int breakpoint = 0;
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unsigned long desc_csr = eval_direct32( channel->regs.desc + DMA_DESC_CSR, 0, 0 );
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unsigned long desc_csr = eval_direct32( channel->regs.desc + DMA_DESC_CSR, &breakpoint, 0, 0 );
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|
|
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channel->load_next_descriptor_when_done = !TEST_FLAG( desc_csr, DMA_DESC_CSR, EOL );
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channel->load_next_descriptor_when_done = !TEST_FLAG( desc_csr, DMA_DESC_CSR, EOL );
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|
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ASSIGN_FLAG( channel->regs.csr, DMA_CH_CSR, INC_SRC, TEST_FLAG( desc_csr, DMA_DESC_CSR, INC_SRC ) );
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ASSIGN_FLAG( channel->regs.csr, DMA_CH_CSR, INC_SRC, TEST_FLAG( desc_csr, DMA_DESC_CSR, INC_SRC ) );
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ASSIGN_FLAG( channel->regs.csr, DMA_CH_CSR, INC_DST, TEST_FLAG( desc_csr, DMA_DESC_CSR, INC_DST ) );
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ASSIGN_FLAG( channel->regs.csr, DMA_CH_CSR, INC_DST, TEST_FLAG( desc_csr, DMA_DESC_CSR, INC_DST ) );
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ASSIGN_FLAG( channel->regs.csr, DMA_CH_CSR, SRC_SEL, TEST_FLAG( desc_csr, DMA_DESC_CSR, SRC_SEL ) );
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ASSIGN_FLAG( channel->regs.csr, DMA_CH_CSR, SRC_SEL, TEST_FLAG( desc_csr, DMA_DESC_CSR, SRC_SEL ) );
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ASSIGN_FLAG( channel->regs.csr, DMA_CH_CSR, DST_SEL, TEST_FLAG( desc_csr, DMA_DESC_CSR, DST_SEL ) );
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ASSIGN_FLAG( channel->regs.csr, DMA_CH_CSR, DST_SEL, TEST_FLAG( desc_csr, DMA_DESC_CSR, DST_SEL ) );
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|
|
SET_FIELD( channel->regs.sz, DMA_CH_SZ, TOT_SZ, GET_FIELD( desc_csr, DMA_DESC_CSR, TOT_SZ ) );
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SET_FIELD( channel->regs.sz, DMA_CH_SZ, TOT_SZ, GET_FIELD( desc_csr, DMA_DESC_CSR, TOT_SZ ) );
|
|
|
channel->regs.a0 = eval_direct32( channel->regs.desc + DMA_DESC_ADR0, &breakpoint, 0, 0 );
|
channel->regs.a0 = eval_direct32( channel->regs.desc + DMA_DESC_ADR0, 0, 0 );
|
channel->regs.a1 = eval_direct32( channel->regs.desc + DMA_DESC_ADR1, &breakpoint, 0, 0 );
|
channel->regs.a1 = eval_direct32( channel->regs.desc + DMA_DESC_ADR1, 0, 0 );
|
|
|
channel->current_descriptor = channel->regs.desc;
|
channel->current_descriptor = channel->regs.desc;
|
channel->regs.desc = eval_direct32( channel->regs.desc + DMA_DESC_NEXT, &breakpoint, 0, 0 );
|
channel->regs.desc = eval_direct32( channel->regs.desc + DMA_DESC_NEXT, 0, 0 );
|
}
|
}
|
|
|
|
|
/* Initialize internal parameters used to implement transfers */
|
/* Initialize internal parameters used to implement transfers */
|
void dma_init_transfer( struct dma_channel *channel )
|
void dma_init_transfer( struct dma_channel *channel )
|
