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Line 22... |
section mc
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section mc
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enable = 1
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enable = 1
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POC = 0x13243545
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POC = 0x13243545
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end
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end
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Simulates only bank switching.
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Limitations:
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- memory refresh is not simulated
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*/
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*/
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#include "mc.h"
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#include "mc.h"
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#include "abstract.h"
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#include "abstract.h"
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#include "sim-config.h"
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static struct mc mc;
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void set_csc_tms (int i, unsigned long csc, unsigned long tms) {
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if (1);
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}
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/* Set a specific MC register with value. */
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void mc_write_word(unsigned long addr, unsigned long value)
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{
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int chipsel;
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debug("mc_write_word(%x,%08x)\n", addr, (unsigned)value);
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addr -= config.mc.baseaddr;
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switch (addr) {
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case MC_CSR:
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mc.csr = value;
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break;
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case MC_POC:
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fprintf (stderr, "warning: write to MC's POC register!");
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break;
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case MC_BA_MASK:
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mc.ba_mask = value;
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break;
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default:
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if (addr >= MC_CSC(0) && addr <= MC_TMS(N_CE - 1)) {
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addr -= MC_CSC(0);
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if ((addr >> 2) & 1)
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mc.tms[addr >> 3] = value;
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else
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mc.csc[addr >> 3] = value;
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set_csc_tms (addr >> 3, mc.csc[addr >> 3], mc.tms[addr >> 3]);
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break;
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} else
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debug("write out of range (addr %x)\n", addr + config.mc.baseaddr);
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}
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}
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/* Read a specific MC register. */
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unsigned long mc_read_word(unsigned long addr)
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{
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unsigned char value = 0;
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int chipsel;
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debug("mc_read_word(%x)\n", addr);
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addr -= config.mc.baseaddr;
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switch (addr) {
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case MC_CSR:
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value = mc.csr;
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break;
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case MC_POC:
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value = mc.poc;
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break;
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case MC_BA_MASK:
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value = mc.ba_mask;
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break;
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default:
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if (addr >= MC_CSC(0) && addr <= MC_TMS(N_CE - 1)) {
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addr -= MC_CSC(0);
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if ((addr >> 2) & 1)
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value = mc.tms[addr >> 3];
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else
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value = mc.csc[addr >> 3];
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} else
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debug("read out of range (addr %x)\n", addr + config.mc.baseaddr);
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break;
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}
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return value;
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}
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/* Read POC register and init memory controler regs. */
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void mc_reset()
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{
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if (config.mc.enabled) {
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printf("Resetting memory controller.\n");
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memset(&mc, 0, sizeof(struct mc));
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mc.poc = config.mc.POC;
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register_memoryarea(config.mc.baseaddr, MC_ADDR_SPACE, 4, mc_read_word, mc_write_word);
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}
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}
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inline void mc_clock()
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{
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}
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No newline at end of file
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No newline at end of file
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