| Line 103... |
Line 103... |
#define SPR_DMR2 (SPRGROUP_D + 17)
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#define SPR_DMR2 (SPRGROUP_D + 17)
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#define SPR_DWCR0 (SPRGROUP_D + 18)
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#define SPR_DWCR0 (SPRGROUP_D + 18)
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#define SPR_DWCR1 (SPRGROUP_D + 19)
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#define SPR_DWCR1 (SPRGROUP_D + 19)
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#define SPR_DSR (SPRGROUP_D + 20)
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#define SPR_DSR (SPRGROUP_D + 20)
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#define SPR_DRR (SPRGROUP_D + 21)
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#define SPR_DRR (SPRGROUP_D + 21)
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#define SPR_DIR (SPRGROUP_D + 22)
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/* Performance counters group */
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/* Performance counters group */
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#define SPR_PCCR(N) (SPRGROUP_PC + (N))
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#define SPR_PCCR(N) (SPRGROUP_PC + (N))
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#define SPR_PCMR(N) (SPRGROUP_PC + 8 + (N))
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#define SPR_PCMR(N) (SPRGROUP_PC + 8 + (N))
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| Line 263... |
Line 262... |
#define SPR_DCR_DP 0x00000001 /* DVR/DCR present */
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#define SPR_DCR_DP 0x00000001 /* DVR/DCR present */
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#define SPR_DCR_CC 0x0000000e /* Compare condition */
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#define SPR_DCR_CC 0x0000000e /* Compare condition */
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#define SPR_DCR_SC 0x00000010 /* Signed compare */
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#define SPR_DCR_SC 0x00000010 /* Signed compare */
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#define SPR_DCR_CT 0x000000e0 /* Compare to */
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#define SPR_DCR_CT 0x000000e0 /* Compare to */
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/* Bit results with SPR_DCR_CC mask */
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#define SPR_DCR_CC_MASKED 0x00000000
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#define SPR_DCR_CC_EQUAL 0x00000001
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#define SPR_DCR_CC_LESS 0x00000002
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#define SPR_DCR_CC_LESSE 0x00000003
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#define SPR_DCR_CC_GREAT 0x00000004
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#define SPR_DCR_CC_GREATE 0x00000005
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#define SPR_DCR_CC_NEQUAL 0x00000006
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/* Bit results with SPR_DCR_CT mask */
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#define SPR_DCR_CT_DISABLED 0x00000000
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#define SPR_DCR_CT_IFEA 0x00000020
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#define SPR_DCR_CT_LEA 0x00000040
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#define SPR_DCR_CT_SEA 0x00000060
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#define SPR_DCR_CT_LD 0x00000080
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#define SPR_DCR_CT_SD 0x000000a0
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#define SPR_DCR_CT_LSEA 0x000000c0
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/*
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/*
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* Bit definitions for Debug Mode 1 register
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* Bit definitions for Debug Mode 1 register
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*
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*
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*/
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*/
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#define SPR_DMR1_CW0 0x00000003 /* Chain watchpoint 0 */
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#define SPR_DMR1_CW0 0x00000003 /* Chain watchpoint 0 */
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Line 331... |
#define SPR_DSR_HPINTE 0x00000080 /* High priority interrupt exception */
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#define SPR_DSR_HPINTE 0x00000080 /* High priority interrupt exception */
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#define SPR_DSR_DME 0x00000100 /* DTLB miss exception */
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#define SPR_DSR_DME 0x00000100 /* DTLB miss exception */
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#define SPR_DSR_IME 0x00000200 /* ITLB miss exception */
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#define SPR_DSR_IME 0x00000200 /* ITLB miss exception */
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#define SPR_DSR_RE 0x00000400 /* Range exception */
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#define SPR_DSR_RE 0x00000400 /* Range exception */
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#define SPR_DSR_SCE 0x00000800 /* System call exception */
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#define SPR_DSR_SCE 0x00000800 /* System call exception */
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#define SPR_DSR_BE 0x00001000 /* Breakpoint exception */
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#define SPR_DSR_SSE 0x00001000 /* Single Step Exception */
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#define SPR_DSR_TE 0x00002000 /* Trap exception */
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/*
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/*
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* Bit definitions for Debug reason register
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* Bit definitions for Debug reason register
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*
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*
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*/
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*/
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| Line 332... |
Line 350... |
#define SPR_DRR_HPINTE 0x00000080 /* High priority interrupt exception */
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#define SPR_DRR_HPINTE 0x00000080 /* High priority interrupt exception */
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#define SPR_DRR_DME 0x00000100 /* DTLB miss exception */
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#define SPR_DRR_DME 0x00000100 /* DTLB miss exception */
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#define SPR_DRR_IME 0x00000200 /* ITLB miss exception */
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#define SPR_DRR_IME 0x00000200 /* ITLB miss exception */
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#define SPR_DRR_RE 0x00000400 /* Range exception */
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#define SPR_DRR_RE 0x00000400 /* Range exception */
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#define SPR_DRR_SCE 0x00000800 /* System call exception */
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#define SPR_DRR_SCE 0x00000800 /* System call exception */
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#define SPR_DRR_BE 0x00001000 /* Breakpoint exception */
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#define SPR_DRR_TE 0x00001000 /* Trap exception */
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/*
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/*
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* Bit definitions for Performance counters mode registers
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* Bit definitions for Performance counters mode registers
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*
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*
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*/
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*/
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