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[/] [or1k/] [tags/] [stable_0_2_0_rc2/] [or1ksim/] [cpu/] [or32/] [insnset.c] - Diff between revs 1508 and 1513

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Rev 1508 Rev 1513
Line 26... Line 26... 
  temp3 = (orreg_t)PARAM1;
 
  temp3 = (orreg_t)PARAM1;
 
  temp1 = temp2 + temp3;
 
  temp1 = temp2 + temp3;
 
  SET_PARAM0(temp1);
 
  SET_PARAM0(temp1);
 
  set_ov_flag (temp1);
 
  set_ov_flag (temp1);
 
  if (ARITH_SET_FLAG) {
 
  if (ARITH_SET_FLAG) {
 
    flag = temp1 == 0;
 
    if(!temp1)
 
    if(flag)
 
 
 
      cpu_state.sprs[SPR_SR] |= SPR_SR_F;
 
      cpu_state.sprs[SPR_SR] |= SPR_SR_F;
 
    else
 
    else
 
      cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
 
      cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
 
  }
 
  }
 
  if ((uorreg_t) temp1 < (uorreg_t) temp2)
 
  if ((uorreg_t) temp1 < (uorreg_t) temp2)
Line 53... Line 52... 
  if(cpu_state.sprs[SPR_SR] & SPR_SR_CY)
 
  if(cpu_state.sprs[SPR_SR] & SPR_SR_CY)
 
    temp1++;
 
    temp1++;
 
  SET_PARAM0(temp1);
 
  SET_PARAM0(temp1);
 
  set_ov_flag (temp1);
 
  set_ov_flag (temp1);
 
  if (ARITH_SET_FLAG) {
 
  if (ARITH_SET_FLAG) {
 
    flag = temp1 == 0;
 
    if(!temp1)
 
    if(flag)
 
 
 
      cpu_state.sprs[SPR_SR] |= SPR_SR_F;
 
      cpu_state.sprs[SPR_SR] |= SPR_SR_F;
 
    else
 
    else
 
      cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
 
      cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
 
  }
 
  }
 
  if ((uorreg_t) temp1 < (uorreg_t) temp2)
 
  if ((uorreg_t) temp1 < (uorreg_t) temp2)
Line 147... Line 145... 
  uorreg_t temp1;
 
  uorreg_t temp1;
 
  temp1 = PARAM1 & PARAM2;
 
  temp1 = PARAM1 & PARAM2;
 
  set_ov_flag (temp1);
 
  set_ov_flag (temp1);
 
  SET_PARAM0(temp1);
 
  SET_PARAM0(temp1);
 
  if (ARITH_SET_FLAG) {
 
  if (ARITH_SET_FLAG) {
 
    flag = temp1 == 0;
 
    if(!temp1)
 
    if(flag)
 
 
 
      cpu_state.sprs[SPR_SR] |= SPR_SR_F;
 
      cpu_state.sprs[SPR_SR] |= SPR_SR_F;
 
    else
 
    else
 
      cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
 
      cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
 
  }
 
  }
 
}
 
}
Line 238... Line 235... 
  /* runtime.sim.cycles += 2; */
 
  /* runtime.sim.cycles += 2; */
 
}
 
}
 
INSTRUCTION (l_bf) {
 
INSTRUCTION (l_bf) {
 
  if (config.bpb.enabled) {
 
  if (config.bpb.enabled) {
 
    int fwd = (PARAM0 >= cpu_state.pc) ? 1 : 0;
 
    int fwd = (PARAM0 >= cpu_state.pc) ? 1 : 0;
 
    or1k_mstats.bf[flag][fwd]++;
 
    or1k_mstats.bf[cpu_state.sprs[SPR_SR] & SPR_SR_F ? 1 : 0][fwd]++;
 
    bpb_update(current->insn_addr, flag);
 
    bpb_update(current->insn_addr, cpu_state.sprs[SPR_SR] & SPR_SR_F ? 1 : 0);
 
  }
 
  }
 
  if (flag) {
 
  if(cpu_state.sprs[SPR_SR] & SPR_SR_F) {
 
    cpu_state.pc_delay = cpu_state.pc + (orreg_t)PARAM0 * 4;
 
    cpu_state.pc_delay = cpu_state.pc + (orreg_t)PARAM0 * 4;
 
    btic_update(pcnext);
 
    btic_update(pcnext);
 
    next_delay_insn = 1;
 
    next_delay_insn = 1;
 
  } else {
 
  } else {
 
    btic_update(cpu_state.pc);
 
    btic_update(cpu_state.pc);
 
  }
 
  }
 
}
 
}
 
INSTRUCTION (l_bnf) {
 
INSTRUCTION (l_bnf) {
 
  if (config.bpb.enabled) {
 
  if (config.bpb.enabled) {
 
    int fwd = (PARAM0 >= cpu_state.pc) ? 1 : 0;
 
    int fwd = (PARAM0 >= cpu_state.pc) ? 1 : 0;
 
    or1k_mstats.bnf[!flag][fwd]++;
 
    or1k_mstats.bnf[cpu_state.sprs[SPR_SR] & SPR_SR_F ? 0 : 1][fwd]++;
 
    bpb_update(current->insn_addr, flag == 0);
 
    bpb_update(current->insn_addr, cpu_state.sprs[SPR_SR] & SPR_SR_F ? 0 : 1);
 
  }
 
  }
 
  if (flag == 0) {
 
  if (!(cpu_state.sprs[SPR_SR] & SPR_SR_F)) {
 
    cpu_state.pc_delay = cpu_state.pc + (orreg_t)PARAM0 * 4;
 
    cpu_state.pc_delay = cpu_state.pc + (orreg_t)PARAM0 * 4;
 
    btic_update(pcnext);
 
    btic_update(pcnext);
 
    next_delay_insn = 1;
 
    next_delay_insn = 1;
 
  } else {
 
  } else {
 
    btic_update(cpu_state.pc);
 
    btic_update(cpu_state.pc);
Line 342... Line 339... 
             evalsim_reg(3));
 
             evalsim_reg(3));
 
      break;
 
      break;
 
  }
 
  }
 
}
 
}
 
INSTRUCTION (l_sfeq) {
 
INSTRUCTION (l_sfeq) {
 
  flag = PARAM0 == PARAM1;
 
  if(PARAM0 == PARAM1)
 
  if(flag)
 
 
 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
 
  else
 
  else
 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
 
}
 
}
 
INSTRUCTION (l_sfne) {
 
INSTRUCTION (l_sfne) {
 
  flag = PARAM0 != PARAM1;
 
  if(PARAM0 != PARAM1)
 
  if(flag)
 
 
 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
 
  else
 
  else
 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
 
}
 
}
 
INSTRUCTION (l_sfgts) {
 
INSTRUCTION (l_sfgts) {
 
  flag = (orreg_t)PARAM0 > (orreg_t)PARAM1;
 
  if((orreg_t)PARAM0 > (orreg_t)PARAM1)
 
  if(flag)
 
 
 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
 
  else
 
  else
 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
 
}
 
}
 
INSTRUCTION (l_sfges) {
 
INSTRUCTION (l_sfges) {
 
  flag = (orreg_t)PARAM0 >= (orreg_t)PARAM1;
 
  if((orreg_t)PARAM0 >= (orreg_t)PARAM1)
 
  if(flag)
 
 
 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
 
  else
 
  else
 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
 
}
 
}
 
INSTRUCTION (l_sflts) {
 
INSTRUCTION (l_sflts) {
 
  flag = (orreg_t)PARAM0 < (orreg_t)PARAM1;
 
  if((orreg_t)PARAM0 < (orreg_t)PARAM1)
 
  if(flag)
 
 
 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
 
  else
 
  else
 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
 
}
 
}
 
INSTRUCTION (l_sfles) {
 
INSTRUCTION (l_sfles) {
 
  flag = (orreg_t)PARAM0 <= (orreg_t)PARAM1;
 
  if((orreg_t)PARAM0 <= (orreg_t)PARAM1)
 
  if(flag)
 
 
 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
 
  else
 
  else
 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
 
}
 
}
 
INSTRUCTION (l_sfgtu) {
 
INSTRUCTION (l_sfgtu) {
 
  flag = PARAM0 > PARAM1;
 
  if(PARAM0 > PARAM1)
 
  if(flag)
 
 
 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
 
  else
 
  else
 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
 
}
 
}
 
INSTRUCTION (l_sfgeu) {
 
INSTRUCTION (l_sfgeu) {
 
  flag = PARAM0 >= PARAM1;
 
  if(PARAM0 >= PARAM1)
 
  if(flag)
 
 
 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
 
  else
 
  else
 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
 
}
 
}
 
INSTRUCTION (l_sfltu) {
 
INSTRUCTION (l_sfltu) {
 
  flag = PARAM0 < PARAM1;
 
  if(PARAM0 < PARAM1)
 
  if(flag)
 
 
 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
 
  else
 
  else
 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
 
}
 
}
 
INSTRUCTION (l_sfleu) {
 
INSTRUCTION (l_sfleu) {
 
  flag = PARAM0 <= PARAM1;
 
  if(PARAM0 <= PARAM1)
 
  if(flag)
 
 
 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
 
  else
 
  else
 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
 
}
 
}
 
INSTRUCTION (l_extbs) {
 
INSTRUCTION (l_extbs) {
Line 535... Line 522... 
  SET_PARAM0((orreg_t)l);
 
  SET_PARAM0((orreg_t)l);
 
  cpu_state.sprs[SPR_MACLO] = 0;
 
  cpu_state.sprs[SPR_MACLO] = 0;
 
  cpu_state.sprs[SPR_MACHI] = 0;
 
  cpu_state.sprs[SPR_MACHI] = 0;
 
}
 
}
 
INSTRUCTION (l_cmov) {
 
INSTRUCTION (l_cmov) {
 
  SET_PARAM0(flag ? PARAM1 : PARAM2);
 
  SET_PARAM0(cpu_state.sprs[SPR_SR] & SPR_SR_F ? PARAM1 : PARAM2);
 
}
 
}
 
INSTRUCTION (l_ff1) {
 
INSTRUCTION (l_ff1) {
 
  SET_PARAM0(ffs(PARAM1));
 
  SET_PARAM0(ffs(PARAM1));
 
}
 
}
 
/******* Floating point instructions *******/
 
/******* Floating point instructions *******/
Line 565... Line 552... 
INSTRUCTION (lf_rem_s) {
 
INSTRUCTION (lf_rem_s) {
 
  float temp = (float)PARAM1 / (float)PARAM2;
 
  float temp = (float)PARAM1 / (float)PARAM2;
 
  SET_PARAM0(temp - (uint32_t)temp);
 
  SET_PARAM0(temp - (uint32_t)temp);
 
}
 
}
 
INSTRUCTION (lf_sfeq_s) {
 
INSTRUCTION (lf_sfeq_s) {
 
  flag = (float)PARAM0 == (float)PARAM1;
 
  if((float)PARAM0 == (float)PARAM1)
 
  if(flag)
 
 
 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
 
  else
 
  else
 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
 
}
 
}
 
INSTRUCTION (lf_sfge_s) {
 
INSTRUCTION (lf_sfge_s) {
 
  flag = (float)PARAM0 >= (float)PARAM1;
 
  if((float)PARAM0 >= (float)PARAM1)
 
  if(flag)
 
 
 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
 
  else
 
  else
 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
 
}
 
}
 
INSTRUCTION (lf_sfgt_s) {
 
INSTRUCTION (lf_sfgt_s) {
 
  flag = (float)PARAM0 > (float)PARAM1;
 
  if((float)PARAM0 > (float)PARAM1)
 
  if(flag)
 
 
 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
 
  else
 
  else
 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
 
}
 
}
 
INSTRUCTION (lf_sfle_s) {
 
INSTRUCTION (lf_sfle_s) {
 
  flag = (float)PARAM0 <= (float)PARAM1;
 
  if((float)PARAM0 <= (float)PARAM1)
 
  if(flag)
 
 
 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
 
  else
 
  else
 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
 
}
 
}
 
INSTRUCTION (lf_sflt_s) {
 
INSTRUCTION (lf_sflt_s) {
 
  flag = (float)PARAM0 < (float)PARAM1;
 
  if((float)PARAM0 < (float)PARAM1)
 
  if(flag)
 
 
 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
 
  else
 
  else
 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
 
}
 
}
 
INSTRUCTION (lf_sfne_s) {
 
INSTRUCTION (lf_sfne_s) {
 
  flag = (float)PARAM0 != (float)PARAM1;
 
  if((float)PARAM0 != (float)PARAM1)
 
  if(flag)
 
 
 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
 
    cpu_state.sprs[SPR_SR] |= SPR_SR_F;
 
  else
 
  else
 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
 
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
 
}
 
}
 
INSTRUCTION (lf_sub_s) {
 
INSTRUCTION (lf_sub_s) {

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