| Line 127... |
Line 127... |
for (nm = 0; nm < f->nmsched; nm++) if (f->msched[nm] == REF (b, i)) break;
|
for (nm = 0; nm < f->nmsched; nm++) if (f->msched[nm] == REF (b, i)) break;
|
assert (nm < f->nmsched);
|
assert (nm < f->nmsched);
|
|
|
GEN (" if (l_end[%i]) t%x_%x <= #Tp ", nls, b, i);
|
GEN (" if (l_end[%i]) t%x_%x <= #Tp ", nls, b, i);
|
switch (f->mtype[nm] & (MT_WIDTH | MT_SIGNED)) {
|
switch (f->mtype[nm] & (MT_WIDTH | MT_SIGNED)) {
|
case 1: GEN ("lwb_dat_i & 32'hff;\n");
|
case 1: GEN ("l_dat_i & 32'hff;\n");
|
break;
|
break;
|
case 2: GEN ("lwb_dat_i & 32'hffff;\n");
|
case 2: GEN ("l_dat_i & 32'hffff;\n");
|
break;
|
break;
|
case 4 | MT_SIGNED:
|
case 4 | MT_SIGNED:
|
case 4: GEN ("lwb_dat_i;\n");
|
case 4: GEN ("l_dat_i;\n");
|
break;
|
break;
|
case 1 | MT_SIGNED:
|
case 1 | MT_SIGNED:
|
GEN ("{24{lwb_dat_i[7]}, lwb_dat_i[7:0]};\n");
|
GEN ("{24{l_dat_i[7]}, l_dat_i[7:0]};\n");
|
break;
|
break;
|
case 2 | MT_SIGNED:
|
case 2 | MT_SIGNED:
|
GEN ("{16{lwb_dat_i[15]}, lwb_dat_i[15:0]};\n");
|
GEN ("{16{l_dat_i[15]}, l_dat_i[15:0]};\n");
|
break;
|
break;
|
default: assert (0);
|
default: assert (0);
|
}
|
}
|
}
|
}
|
} else if (ii->index == II_LRBB) {
|
} else if (ii->index == II_LRBB) {
|
| Line 234... |
Line 234... |
GEN (" at %08x - %08x\n", f->start_addr, f->end_addr);
|
GEN (" at %08x - %08x\n", f->start_addr, f->end_addr);
|
GEN (" num BBs %i */\n\n", f->num_bb);
|
GEN (" num BBs %i */\n\n", f->num_bb);
|
|
|
GEN ("`include \"timescale.v\"\n\n");
|
GEN ("`include \"timescale.v\"\n\n");
|
GEN ("module %s (clk, rst,\n", filename);
|
GEN ("module %s (clk, rst,\n", filename);
|
GEN (" lwb_adr_o, lwb_dat_i, lwb_cycstb_o,\n");
|
GEN (" l_adr_o, l_dat_i, l_req_o,\n");
|
GEN (" lwb_sel_o, lwb_linbrst_o, lwb_ack_i,\n");
|
GEN (" l_sel_o, l_linbrst_o, l_rdy_i,\n");
|
GEN (" swb_adr_o, swb_dat_o, swb_cycstb_o,\n");
|
GEN (" s_adr_o, s_dat_o, s_req_o,\n");
|
GEN (" swb_sel_o, swb_linbrst_o, swb_ack_i,\n");
|
GEN (" s_sel_o, s_linbrst_o, s_rdy_i,\n");
|
|
|
GEN ("/* inputs */ ");
|
GEN ("/* inputs */ ");
|
for (i = 0; i < MAX_REGS; i++)
|
for (i = 0; i < MAX_REGS; i++)
|
if (f->used_regs[i]) {
|
if (f->used_regs[i]) {
|
GEN ("r%i_i, ", i);
|
GEN ("r%i_i, ", i);
|
| Line 269... |
Line 269... |
GEN ("input clk, rst;\n");
|
GEN ("input clk, rst;\n");
|
GEN ("input start_i;\t/* Module starts when set to 1 */ \n");
|
GEN ("input start_i;\t/* Module starts when set to 1 */ \n");
|
GEN ("output end_o;\t/* Set when module finishes, cleared upon start_i == 1 */\n");
|
GEN ("output end_o;\t/* Set when module finishes, cleared upon start_i == 1 */\n");
|
GEN ("output busy_o;\t/* Set when module should not be interrupted */\n");
|
GEN ("output busy_o;\t/* Set when module should not be interrupted */\n");
|
GEN ("\n/* Bus signals */\n");
|
GEN ("\n/* Bus signals */\n");
|
GEN ("output lwb_cycstb_o, swb_cycstb_o;\n");
|
GEN ("output l_req_o, s_req_o;\n");
|
GEN ("input lwb_ack_i, swb_ack_i;\n");
|
GEN ("input l_rdy_i, s_rdy_i;\n");
|
GEN ("output [3:0] lwb_sel_o, swb_sel_o;\n");
|
GEN ("output [3:0] l_sel_o, s_sel_o;\n");
|
GEN ("output [31:0] lwb_adr_o, swb_adr_o;\n");
|
GEN ("output [31:0] l_adr_o, s_adr_o;\n");
|
GEN ("output lwb_linbrst_o, swb_linbrst_o;\n");
|
GEN ("output l_linbrst_o, s_linbrst_o;\n");
|
GEN ("input [31:0] lwb_dat_i;\n");
|
GEN ("input [31:0] l_dat_i;\n");
|
GEN ("output [31:0] swb_dat_o;\n\n");
|
GEN ("output [31:0] s_dat_o;\n\n");
|
|
|
GEN ("reg lwb_cycstb_o, swb_cycstb_o;\n");
|
GEN ("reg l_req_o, s_req_o;\n");
|
GEN ("reg [31:0] lwb_adr_o, swb_adr_o;\n");
|
GEN ("reg [31:0] l_adr_o, s_adr_o;\n");
|
GEN ("reg [3:0] lwb_sel_o, swb_sel_o;\n");
|
GEN ("reg [3:0] l_sel_o, s_sel_o;\n");
|
GEN ("reg [31:0] swb_dat_o;\n");
|
GEN ("reg [31:0] s_dat_o;\n");
|
GEN ("reg lwb_linbrst_o, swb_linbrst_o;\n");
|
GEN ("reg l_linbrst_o, s_linbrst_o;\n");
|
|
|
if (ci || co) GEN ("\n/* module ports */\n");
|
if (ci || co) GEN ("\n/* module ports */\n");
|
if (ci) {
|
if (ci) {
|
int first = 1;
|
int first = 1;
|
GEN ("input [31:0]");
|
GEN ("input [31:0]");
|
| Line 438... |
Line 438... |
}
|
}
|
if (!first) GEN (";\n");
|
if (!first) GEN (";\n");
|
}
|
}
|
|
|
if (nloads || nstores) GEN ("\n/* dependencies */\n");
|
if (nloads || nstores) GEN ("\n/* dependencies */\n");
|
if (nloads) GEN ("wire [%i:0] l_end = l_stb & {%i{lwb_ack_i}};\n",
|
if (nloads) GEN ("wire [%i:0] l_end = l_stb & {%i{l_rdy_i}};\n",
|
nloads - 1, nloads);
|
nloads - 1, nloads);
|
if (nstores) GEN ("wire [%i:0] s_end = s_stb & {%i{swb_ack_i}};\n",
|
if (nstores) GEN ("wire [%i:0] s_end = s_stb & {%i{s_rdy_i}};\n",
|
nstores - 1, nstores);
|
nstores - 1, nstores);
|
if (ncalls) GEN ("wire [%i:0] f_end = f_stb & {%i{fend_i}};\n",
|
if (ncalls) GEN ("wire [%i:0] f_end = f_stb & {%i{fend_i}};\n",
|
ncalls - 1, ncalls);
|
ncalls - 1, ncalls);
|
|
|
GEN ("\n/* last dependency */\n");
|
GEN ("\n/* last dependency */\n");
|
| Line 538... |
Line 538... |
|
|
cur_store = 0;
|
cur_store = 0;
|
GEN (")\nbegin\n");
|
GEN (")\nbegin\n");
|
for (i = 0; i < f->nmsched; i++) if (f->mtype[i] & MT_STORE) {
|
for (i = 0; i < f->nmsched; i++) if (f->mtype[i] & MT_STORE) {
|
char t[30];
|
char t[30];
|
GEN (" %sif (s_stb[%i]) swb_dat_o = %s;\n", cur_store == 0 ? "" : "else ", cur_store,
|
GEN (" %sif (s_stb[%i]) s_dat_o = %s;\n", cur_store == 0 ? "" : "else ", cur_store,
|
print_op_v (f, t, f->msched[i], 0));
|
print_op_v (f, t, f->msched[i], 0));
|
cur_store++;
|
cur_store++;
|
//PRINTF ("msched[%i] = %x (mtype %x) %x\n", i, f->msched[i], f->mtype[i], f->INSN(f->msched[i]).op[0]);
|
//PRINTF ("msched[%i] = %x (mtype %x) %x\n", i, f->msched[i], f->mtype[i], f->INSN(f->msched[i]).op[0]);
|
}
|
}
|
GEN (" else swb_dat_o = 32'hx;\n");
|
GEN (" else s_dat_o = 32'hx;\n");
|
GEN ("end\n");
|
GEN ("end\n");
|
}
|
}
|
|
|
/* Generate load and store state machine */
|
/* Generate load and store state machine */
|
for (j = 0; j < 2; j++) {
|
for (j = 0; j < 2; j++) {
|
| Line 604... |
Line 604... |
cucdebug (1, "msched[%i] = %x (mtype %x)\n", i, f->msched[i], f->mtype[i]);
|
cucdebug (1, "msched[%i] = %x (mtype %x)\n", i, f->msched[i], f->mtype[i]);
|
assert (f->INSN(f->msched[i]).opt[1] & (OPT_REF | OPT_REGISTER));
|
assert (f->INSN(f->msched[i]).opt[1] & (OPT_REF | OPT_REGISTER));
|
GEN ("if (");
|
GEN ("if (");
|
print_deps (fo, f, REF_BB(f->msched[i]), f->INSN(f->msched[i]).dep, 1);
|
print_deps (fo, f, REF_BB(f->msched[i]), f->INSN(f->msched[i]).dep, 1);
|
GEN (") begin\n");
|
GEN (") begin\n");
|
GEN (" %cwb_cycstb_o = 1'b1;\n", c);
|
GEN (" %c_req_o = 1'b1;\n", c);
|
GEN (" %cwb_sel_o[3:0] = 4'b", c);
|
GEN (" %c_sel_o[3:0] = 4'b", c);
|
switch (f->mtype[i] & MT_WIDTH) {
|
switch (f->mtype[i] & MT_WIDTH) {
|
case 1: GEN ("0001 << (%s & 32'h3);\n",
|
case 1: GEN ("0001 << (%s & 32'h3);\n",
|
print_op_v (f, t, f->msched[i], 1)); break;
|
print_op_v (f, t, f->msched[i], 1)); break;
|
case 2: GEN ("0011 << ((%s & 32'h1) << 1);\n",
|
case 2: GEN ("0011 << ((%s & 32'h1) << 1);\n",
|
print_op_v (f, t, f->msched[i], 1)); break;
|
print_op_v (f, t, f->msched[i], 1)); break;
|
case 4: GEN ("1111;\n"); break;
|
case 4: GEN ("1111;\n"); break;
|
default: assert (0);
|
default: assert (0);
|
}
|
}
|
GEN (" %cwb_linbrst_o = 1'b%i;\n", c,
|
GEN (" %c_linbrst_o = 1'b%i;\n", c,
|
(f->mtype[i] & MT_BURST) && !(f->mtype[i] & MT_BURSTE) ? 1 : 0);
|
(f->mtype[i] & MT_BURST) && !(f->mtype[i] & MT_BURSTE) ? 1 : 0);
|
GEN (" %cwb_adr_o = t%x_%x & ~32'h3;\n", c,
|
GEN (" %c_adr_o = t%x_%x & ~32'h3;\n", c,
|
REF_BB(f->INSN(f->msched[i]).op[1]), REF_I(f->INSN(f->msched[i]).op[1]));
|
REF_BB(f->INSN(f->msched[i]).op[1]), REF_I(f->INSN(f->msched[i]).op[1]));
|
GEN (" end else ");
|
GEN (" end else ");
|
}
|
}
|
GEN ("if (%c_end[%i]) begin\n", c, cur - 1);
|
GEN ("if (%c_end[%i]) begin\n", c, cur - 1);
|
GEN (" %cwb_cycstb_o = 1'b0;\n", c);
|
GEN (" %c_req_o = 1'b0;\n", c);
|
GEN (" %cwb_sel_o[3:0] = 4'bx;\n", c);
|
GEN (" %c_sel_o[3:0] = 4'bx;\n", c);
|
GEN (" %cwb_linbrst_o = 1'b0;\n", c);
|
GEN (" %c_linbrst_o = 1'b0;\n", c);
|
GEN (" %cwb_adr_o = 32'hx;\n", c);
|
GEN (" %c_adr_o = 32'hx;\n", c);
|
GEN (" end else begin\n");
|
GEN (" end else begin\n");
|
GEN (" %cwb_cycstb_o = 1'b0;\n", c);
|
GEN (" %c_req_o = 1'b0;\n", c);
|
GEN (" %cwb_sel_o[3:0] = 4'bx;\n", c);
|
GEN (" %c_sel_o[3:0] = 4'bx;\n", c);
|
GEN (" %cwb_linbrst_o = 1'b0;\n", c);
|
GEN (" %c_linbrst_o = 1'b0;\n", c);
|
GEN (" %cwb_adr_o = 32'hx;\n", c);
|
GEN (" %c_adr_o = 32'hx;\n", c);
|
GEN (" end\n");
|
GEN (" end\n");
|
GEN ("end\n");
|
GEN ("end\n");
|
}
|
}
|
}
|
}
|
|
|
| Line 741... |
Line 741... |
GEN (" */\n\n");
|
GEN (" */\n\n");
|
|
|
GEN ("`include \"timescale.v\"\n\n");
|
GEN ("`include \"timescale.v\"\n\n");
|
GEN ("module %s (clk, rst,\n", filename);
|
GEN ("module %s (clk, rst,\n", filename);
|
GEN (" /* Load and store master Wishbone ports */\n");
|
GEN (" /* Load and store master Wishbone ports */\n");
|
GEN (" lwb_adr_o, lwb_dat_i, lwb_cyc_o, lwb_stb_o,\n");
|
GEN (" l_adr_o, l_dat_i, l_cyc_o, l_stb_o,\n");
|
GEN (" lwb_sel_o, lwb_linbrst_o, lwb_ack_i, lwb_we_o,\n");
|
GEN (" l_sel_o, l_linbrst_o, l_rdy_i, l_we_o,\n");
|
GEN (" swb_adr_o, swb_dat_o, swb_cyc_o, swb_stb_o,\n");
|
GEN (" s_adr_o, s_dat_o, s_cyc_o, s_stb_o,\n");
|
GEN (" swb_sel_o, swb_linbrst_o, swb_ack_i, swb_we_o,\n\n");
|
GEN (" s_sel_o, s_linbrst_o, s_rdy_i, s_we_o,\n\n");
|
GEN (" /* cuc interface */\n");
|
GEN (" /* cuc interface */\n");
|
GEN (" cuc_stb_i, cuc_adr_i, cuc_dat_i, cuc_dat_o, cuc_we_i, cuc_ack_o);\n\n");
|
GEN (" cuc_stb_i, cuc_adr_i, cuc_dat_i, cuc_dat_o, cuc_we_i, cuc_rdy_o);\n\n");
|
|
|
GEN ("parameter Tp = 1;\n");
|
GEN ("parameter Tp = 1;\n");
|
GEN ("\n/* module ports */\n");
|
GEN ("\n/* module ports */\n");
|
GEN ("input clk, rst, cuc_stb_i, cuc_we_i;\n");
|
GEN ("input clk, rst, cuc_stb_i, cuc_we_i;\n");
|
GEN ("input lwb_ack_i, swb_ack_i;\n");
|
GEN ("input l_rdy_i, s_rdy_i;\n");
|
GEN ("output lwb_cyc_o, lwb_stb_o, lwb_we_o, lwb_linbrst_o;\n");
|
GEN ("output l_cyc_o, l_stb_o, l_we_o, l_linbrst_o;\n");
|
GEN ("reg lwb_cyc_o, lwb_stb_o, lwb_we_o, lwb_linbrst_o;\n");
|
GEN ("reg l_cyc_o, l_stb_o, l_we_o, l_linbrst_o;\n");
|
GEN ("output swb_cyc_o, swb_stb_o, swb_we_o, swb_linbrst_o;\n");
|
GEN ("output s_cyc_o, s_stb_o, s_we_o, s_linbrst_o;\n");
|
GEN ("reg swb_cyc_o, swb_stb_o, swb_we_o, swb_linbrst_o;\n");
|
GEN ("reg s_cyc_o, s_stb_o, s_we_o, s_linbrst_o;\n");
|
GEN ("output cuc_ack_o; /* Not registered ! */\n");
|
GEN ("output cuc_rdy_o; /* Not registered ! */\n");
|
GEN ("output [3:0] lwb_sel_o, swb_sel_o;\n");
|
GEN ("output [3:0] l_sel_o, s_sel_o;\n");
|
GEN ("reg [3:0] lwb_sel_o, swb_sel_o;\n");
|
GEN ("reg [3:0] l_sel_o, s_sel_o;\n");
|
GEN ("output [31:0] lwb_adr_o, swb_adr_o, swb_dat_o, cuc_dat_o;\n");
|
GEN ("output [31:0] l_adr_o, s_adr_o, s_dat_o, cuc_dat_o;\n");
|
GEN ("reg [31:0] lwb_adr_o, swb_adr_o, swb_dat_o, cuc_dat_o;\n");
|
GEN ("reg [31:0] l_adr_o, s_adr_o, s_dat_o, cuc_dat_o;\n");
|
GEN ("input [15:0] cuc_adr_i;\n");
|
GEN ("input [15:0] cuc_adr_i;\n");
|
GEN ("input [31:0] lwb_dat_i, cuc_dat_i;\n\n");
|
GEN ("input [31:0] l_dat_i, cuc_dat_i;\n\n");
|
|
|
GEN ("wire [%2i:0] i_we, i_re, i_finish, i_selected, i_first_reg;\n", nrf - 1);
|
GEN ("wire [%2i:0] i_we, i_re, i_finish, i_selected, i_first_reg;\n", nrf - 1);
|
GEN ("wire [%2i:0] i_bidok, i_start_bid, i_start_bidok, main_start, main_end;\n", nrf - 1);
|
GEN ("wire [%2i:0] i_bidok, i_start_bid, i_start_bidok, main_start, main_end;\n", nrf - 1);
|
GEN ("wire [%2i:0] i_start, i_end, i_start_block, i_busy;\n", nrf - 1);
|
GEN ("wire [%2i:0] i_start, i_end, i_start_block, i_busy;\n", nrf - 1);
|
GEN ("wire [%2i:0] i_lwb_cycstb, i_swb_cycstb;\n", nrf - 1);
|
GEN ("wire [%2i:0] i_l_req, i_s_req;\n", nrf - 1);
|
GEN ("reg [%2i:0] i_go_bsy, main_start_r;\n", nrf - 1);
|
GEN ("reg [%2i:0] i_go_bsy, main_start_r;\n", nrf - 1);
|
|
|
GEN ("assign i_selected = {\n");
|
GEN ("assign i_selected = {\n");
|
for (i = 0; i < nrf; i++)
|
for (i = 0; i < nrf; i++)
|
GEN (" cuc_adr_i[15:6] == %i%s\n", i, i < nrf - 1 ? "," : "};");
|
GEN (" cuc_adr_i[15:6] == %i%s\n", i, i < nrf - 1 ? "," : "};");
|
| Line 783... |
Line 783... |
}
|
}
|
|
|
GEN ("assign i_we = {%i{cuc_stb_i && cuc_we_i}} & i_selected;\n", nrf);
|
GEN ("assign i_we = {%i{cuc_stb_i && cuc_we_i}} & i_selected;\n", nrf);
|
GEN ("assign i_re = {%i{cuc_stb_i && !cuc_we_i}} & i_selected;\n", nrf);
|
GEN ("assign i_re = {%i{cuc_stb_i && !cuc_we_i}} & i_selected;\n", nrf);
|
|
|
GEN ("assign i_start = i_go_bsy & {%i{cuc_ack_o}};\n", nrf);
|
GEN ("assign i_start = i_go_bsy & {%i{cuc_rdy_o}};\n", nrf);
|
GEN ("assign i_start_bidok = {\n");
|
GEN ("assign i_start_bidok = {\n");
|
for (i = 0; i < nrf; i++)
|
for (i = 0; i < nrf; i++)
|
GEN (" i_start_bid[%i] < %i%s\n", i, i, i < nrf - 1 ? "," : "};");
|
GEN (" i_start_bid[%i] < %i%s\n", i, i, i < nrf - 1 ? "," : "};");
|
GEN ("assign main_start = i_start & i_selected & i_first_reg & i_we;\n");
|
GEN ("assign main_start = i_start & i_selected & i_first_reg & i_we;\n");
|
GEN ("assign main_end = {%i{i_end}} & i_selected;\n");
|
GEN ("assign main_end = {%i{i_end}} & i_selected;\n");
|
| Line 816... |
Line 816... |
GEN ("%s i%i_r%io", first ? "/* outputs */\nwire [31:0]" : ",", fn, j);
|
GEN ("%s i%i_r%io", first ? "/* outputs */\nwire [31:0]" : ",", fn, j);
|
first = 0;
|
first = 0;
|
co++;
|
co++;
|
}
|
}
|
if (co) GEN (";\n");
|
if (co) GEN (";\n");
|
GEN ("wire [31:0] i%i_lwb_adr, i%i_swb_adr;\n", fn, fn);
|
GEN ("wire [31:0] i%i_l_adr, i%i_s_adr;\n", fn, fn);
|
|
|
GEN ("always @(posedge clk or posedge rst)\n");
|
GEN ("always @(posedge clk or posedge rst)\n");
|
GEN (" if (rst) main_start_r <= #Tp %i'b0;\n", nrf);
|
GEN (" if (rst) main_start_r <= #Tp %i'b0;\n", nrf);
|
GEN (" else main_start_r <= #Tp main_start & i_start_bidok | i_busy | ~i_end & main_start_r;\n");
|
GEN (" else main_start_r <= #Tp main_start & i_start_bidok | i_busy | ~i_end & main_start_r;\n");
|
|
|
| Line 872... |
Line 872... |
}
|
}
|
GEN ("cuc_dat_o <= #Tp 32'hx;\n");
|
GEN ("cuc_dat_o <= #Tp 32'hx;\n");
|
GEN (" end else cuc_dat_o <= #Tp 32'hx;\n");
|
GEN (" end else cuc_dat_o <= #Tp 32'hx;\n");
|
|
|
GEN ("\n/* read register access - acknowledge */\n");
|
GEN ("\n/* read register access - acknowledge */\n");
|
GEN ("assign cuc_ack_o = cuc_stb_i && cuc_we_i && |(i_selected & main_end);\n");
|
GEN ("assign cuc_rdy_o = cuc_stb_i && cuc_we_i && |(i_selected & main_end);\n");
|
}
|
}
|
|
|
/* Store/load Wishbone bridge */
|
/* Store/load Wishbone bridge */
|
for (j = 0; j < 2; j++) {
|
for (j = 0; j < 2; j++) {
|
char t = j ? 's' : 'l';
|
char t = j ? 's' : 'l';
|
| Line 884... |
Line 884... |
GEN ("reg [%i:0] %cm_sel;\n", log2 (nrf), t);
|
GEN ("reg [%i:0] %cm_sel;\n", log2 (nrf), t);
|
GEN ("reg [%i:0] %cm_bid;\n", log2 (nrf), t);
|
GEN ("reg [%i:0] %cm_bid;\n", log2 (nrf), t);
|
GEN ("reg %ccyc_ip;\n\n", t);
|
GEN ("reg %ccyc_ip;\n\n", t);
|
GEN ("always @(posedge clk)\n");
|
GEN ("always @(posedge clk)\n");
|
GEN ("begin\n");
|
GEN ("begin\n");
|
GEN (" %cwb_we_o <= #Tp 1'b%i;\n", t, j);
|
GEN (" %c_we_o <= #Tp 1'b%i;\n", t, j);
|
GEN (" %cwb_cyc_o <= #Tp |i_%cwb_cycstb;\n", t, t);
|
GEN (" %c_cyc_o <= #Tp |i_%c_req;\n", t, t);
|
GEN (" %cwb_stb_o <= #Tp |i_%cwb_cycstb;\n", t, t);
|
GEN (" %c_stb_o <= #Tp |i_%c_req;\n", t, t);
|
GEN ("end\n");
|
GEN ("end\n");
|
|
|
GEN ("\n/* highest bid */\n");
|
GEN ("\n/* highest bid */\n");
|
GEN ("always @(");
|
GEN ("always @(");
|
for (i = 0; i < nrf; i++) GEN ("%si_%cwb_cycstb", i > 0 ? " or " : "", t);
|
for (i = 0; i < nrf; i++) GEN ("%si_%c_req", i > 0 ? " or " : "", t);
|
GEN (")\n");
|
GEN (")\n");
|
for (i = 0; i < nrf; i++) GEN (" %sif (i_%cwb_cycstb) %cm_bid = %i'h%x;\n",
|
for (i = 0; i < nrf; i++) GEN (" %sif (i_%c_req) %cm_bid = %i'h%x;\n",
|
i ? "else " : "", t, t, log2 (nrf) + 1, i);
|
i ? "else " : "", t, t, log2 (nrf) + 1, i);
|
|
|
GEN ("\n/* selected transfer */\n");
|
GEN ("\n/* selected transfer */\n");
|
GEN ("always @(posedge clk or posedge rst)\n");
|
GEN ("always @(posedge clk or posedge rst)\n");
|
GEN (" if (rst) %cm_sel <= #Tp %i'h0;\n", t, log2 (nrf) + 1);
|
GEN (" if (rst) %cm_sel <= #Tp %i'h0;\n", t, log2 (nrf) + 1);
|
GEN (" else if (%cwb_ack_i) %cm_sel <= #Tp %i'h0;\n", t, t, log2 (nrf) + 1);
|
GEN (" else if (%c_rdy_i) %cm_sel <= #Tp %i'h0;\n", t, t, log2 (nrf) + 1);
|
GEN (" else if (!%ccyc_ip) %cm_sel <= #Tp %cm_bid;\n", t, t, t);
|
GEN (" else if (!%ccyc_ip) %cm_sel <= #Tp %cm_bid;\n", t, t, t);
|
|
|
GEN ("\n/* Cycle */\n");
|
GEN ("\n/* Cycle */\n");
|
GEN ("\nalways @(posedge clk or posedge rst)\n");
|
GEN ("\nalways @(posedge clk or posedge rst)\n");
|
GEN (" if (rst) %ccyc_ip <= #Tp 1'b0;\n", t);
|
GEN (" if (rst) %ccyc_ip <= #Tp 1'b0;\n", t);
|
GEN (" else if (%cwb_ack_i) %ccyc_ip <= #Tp 1'b0;\n", t, t);
|
GEN (" else if (%c_rdy_i) %ccyc_ip <= #Tp 1'b0;\n", t, t);
|
GEN (" else %ccyc_ip <= #Tp %cwb_cyc_o;\n", t, t);
|
GEN (" else %ccyc_ip <= #Tp %c_cyc_o;\n", t, t);
|
}
|
}
|
|
|
GEN ("\n/* Acknowledge */\n");
|
GEN ("\n/* Acknowledge */\n");
|
for (i = 0; i < nrf; i++) {
|
for (i = 0; i < nrf; i++) {
|
GEN ("wire i%i_swb_ack = ((sm_bid == %i & !scyc_ip) | sm_sel == %i) & swb_ack_i;\n", i, i, i);
|
GEN ("wire i%i_s_rdy = ((sm_bid == %i & !scyc_ip) | sm_sel == %i) & s_rdy_i;\n", i, i, i);
|
GEN ("wire i%i_lwb_ack = ((lm_bid == %i & !lcyc_ip) | lm_sel == %i) & lwb_ack_i;\n", i, i, i);
|
GEN ("wire i%i_l_rdy = ((lm_bid == %i & !lcyc_ip) | lm_sel == %i) & l_rdy_i;\n", i, i, i);
|
}
|
}
|
|
|
GEN ("\n/* data, address selects and burst enables */\n");
|
GEN ("\n/* data, address selects and burst enables */\n");
|
for (i = 0; i < nrf; i++) GEN ("wire [31:0] i%i_swb_dat;\n", i);
|
for (i = 0; i < nrf; i++) GEN ("wire [31:0] i%i_s_dat;\n", i);
|
for (i = 0; i < nrf; i++) GEN ("wire i%i_swb_linbrst, i%i_lwb_linbrst;\n", i, i);
|
for (i = 0; i < nrf; i++) GEN ("wire i%i_s_linbrst, i%i_l_linbrst;\n", i, i);
|
for (i = 0; i < nrf; i++) GEN ("wire [3:0] i%i_swb_sel, i%i_lwb_sel;\n", i, i);
|
for (i = 0; i < nrf; i++) GEN ("wire [3:0] i%i_s_sel, i%i_l_sel;\n", i, i);
|
for (i = 0; i < nrf; i++) GEN ("wire [31:0] i%i_lwb_dat = lwb_dat_i;\n", i);
|
for (i = 0; i < nrf; i++) GEN ("wire [31:0] i%i_l_dat = l_dat_i;\n", i);
|
GEN ("\nalways @(posedge clk)\n");
|
GEN ("\nalways @(posedge clk)\n");
|
GEN ("begin\n");
|
GEN ("begin\n");
|
GEN (" swb_dat_o <= #Tp ");
|
GEN (" s_dat_o <= #Tp ");
|
for (i = 0; i < nrf - 1; i++)
|
for (i = 0; i < nrf - 1; i++)
|
GEN ("\n sm_bid == %i ? i%i_swb_dat : ", i, i);
|
GEN ("\n sm_bid == %i ? i%i_s_dat : ", i, i);
|
GEN ("i%i_swb_dat;\n", nrf - 1);
|
GEN ("i%i_s_dat;\n", nrf - 1);
|
GEN (" swb_adr_o <= #Tp ");
|
GEN (" s_adr_o <= #Tp ");
|
for (i = 0; i < nrf - 1; i++)
|
for (i = 0; i < nrf - 1; i++)
|
GEN ("\n sm_bid == %i ? i%i_swb_adr : ", i, i);
|
GEN ("\n sm_bid == %i ? i%i_s_adr : ", i, i);
|
GEN ("i%i_swb_adr;\n", nrf - 1);
|
GEN ("i%i_s_adr;\n", nrf - 1);
|
GEN (" swb_sel_o <= #Tp ");
|
GEN (" s_sel_o <= #Tp ");
|
for (i = 0; i < nrf - 1; i++)
|
for (i = 0; i < nrf - 1; i++)
|
GEN ("\n sm_bid == %i ? i%i_swb_sel : ", i, i);
|
GEN ("\n sm_bid == %i ? i%i_s_sel : ", i, i);
|
GEN ("i%i_swb_sel;\n", nrf - 1);
|
GEN ("i%i_s_sel;\n", nrf - 1);
|
GEN (" swb_linbrst_o <= #Tp ");
|
GEN (" s_linbrst_o <= #Tp ");
|
for (i = 0; i < nrf - 1; i++)
|
for (i = 0; i < nrf - 1; i++)
|
GEN ("\n sm_bid == %i ? i%i_swb_linbrst : ", i, i);
|
GEN ("\n sm_bid == %i ? i%i_s_linbrst : ", i, i);
|
GEN ("i%i_swb_linbrst;\n", nrf - 1);
|
GEN ("i%i_s_linbrst;\n", nrf - 1);
|
GEN ("end\n\n");
|
GEN ("end\n\n");
|
|
|
GEN ("always @(posedge clk)\n");
|
GEN ("always @(posedge clk)\n");
|
GEN ("begin\n");
|
GEN ("begin\n");
|
GEN (" lwb_adr_o <= #Tp ");
|
GEN (" l_adr_o <= #Tp ");
|
for (i = 0; i < nrf - 1; i++)
|
for (i = 0; i < nrf - 1; i++)
|
GEN ("\n lm_bid == %i ? i%i_lwb_adr : ", i, i);
|
GEN ("\n lm_bid == %i ? i%i_l_adr : ", i, i);
|
GEN ("i%i_lwb_adr;\n", nrf - 1);
|
GEN ("i%i_l_adr;\n", nrf - 1);
|
GEN (" lwb_sel_o <= #Tp ");
|
GEN (" l_sel_o <= #Tp ");
|
for (i = 0; i < nrf - 1; i++)
|
for (i = 0; i < nrf - 1; i++)
|
GEN ("\n lm_bid == %i ? i%i_lwb_sel : ", i, i);
|
GEN ("\n lm_bid == %i ? i%i_l_sel : ", i, i);
|
GEN ("i%i_lwb_sel;\n", nrf - 1);
|
GEN ("i%i_l_sel;\n", nrf - 1);
|
GEN (" lwb_linbrst_o <= #Tp ");
|
GEN (" l_linbrst_o <= #Tp ");
|
for (i = 0; i < nrf - 1; i++)
|
for (i = 0; i < nrf - 1; i++)
|
GEN ("\n lm_bid == %i ? i%i_lwb_linbrst : ", i, i);
|
GEN ("\n lm_bid == %i ? i%i_l_linbrst : ", i, i);
|
GEN ("i%i_lwb_linbrst;\n", nrf - 1);
|
GEN ("i%i_l_linbrst;\n", nrf - 1);
|
GEN ("end\n\n");
|
GEN ("end\n\n");
|
|
|
/* start/end signals */
|
/* start/end signals */
|
GEN ("\n\n/* start/end signals */\n");
|
GEN ("\n\n/* start/end signals */\n");
|
for (i = 0; i < nrf; i++) {
|
for (i = 0; i < nrf; i++) {
|
| Line 986... |
Line 986... |
|
|
for (i = 0; i < nfuncs; i++) if (f[i]) {
|
for (i = 0; i < nfuncs; i++) if (f[i]) {
|
int nf = f[i]->tmp;
|
int nf = f[i]->tmp;
|
GEN ("\n%s%s i%i(.clk(clk), .rst(rst),\n", filename, prof_func[i].name, nf);
|
GEN ("\n%s%s i%i(.clk(clk), .rst(rst),\n", filename, prof_func[i].name, nf);
|
GEN ("");
|
GEN ("");
|
GEN (" .lwb_adr_o(i%i_lwb_adr), .lwb_dat_i(i%i_lwb_dat), .lwb_cycstb_o(i_lwb_cycstb[%i]),\n",
|
GEN (" .l_adr_o(i%i_l_adr), .l_dat_i(i%i_l_dat), .l_req_o(i_l_req[%i]),\n",
|
nf, nf, nf);
|
nf, nf, nf);
|
GEN (" .lwb_sel_o(i%i_lwb_sel), .lwb_linbrst_o(i%i_lwb_linbrst), .lwb_ack_i(i%i_lwb_ack),\n",
|
GEN (" .l_sel_o(i%i_l_sel), .l_linbrst_o(i%i_l_linbrst), .l_rdy_i(i%i_l_rdy),\n",
|
nf, nf, nf);
|
nf, nf, nf);
|
GEN (" .swb_adr_o(i%i_swb_adr), .swb_dat_o(i%i_swb_dat), .swb_cycstb_o(i_swb_cycstb[%i]),\n",
|
GEN (" .s_adr_o(i%i_s_adr), .s_dat_o(i%i_s_dat), .s_req_o(i_s_req[%i]),\n",
|
nf, nf, nf);
|
nf, nf, nf);
|
GEN (" .swb_sel_o(i%i_swb_sel), .swb_linbrst_o(i%i_swb_linbrst), .swb_ack_i(i%i_swb_ack),\n",
|
GEN (" .s_sel_o(i%i_s_sel), .s_linbrst_o(i%i_s_linbrst), .s_rdy_i(i%i_s_rdy),\n",
|
nf, nf, nf);
|
nf, nf, nf);
|
GEN (" ");
|
GEN (" ");
|
for (j = 0, first = 1; j < MAX_REGS; j++) if (f[i]->used_regs[j])
|
for (j = 0, first = 1; j < MAX_REGS; j++) if (f[i]->used_regs[j])
|
GEN (".r%i_i(i%i_r%ii), ", j, nf, j), first = 0;
|
GEN (".r%i_i(i%i_r%ii), ", j, nf, j), first = 0;
|
|
|
