| Line 25... |
Line 25... |
Every attempt has been made to be as accurate as possible with
|
Every attempt has been made to be as accurate as possible with
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respect to the registers and the behavior. There are no known
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respect to the registers and the behavior. There are no known
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limitations at this time.
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limitations at this time.
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*/
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*/
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|
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//#define DEBUG_JTAG 0
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|
|
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#include <stdlib.h>
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#include <stdlib.h>
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#include <stdio.h>
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#include <stdio.h>
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#include <string.h>
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#include <string.h>
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|
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#include "config.h"
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#include "config.h"
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| Line 52... |
Line 50... |
#include "spr_defs.h"
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#include "spr_defs.h"
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#include "execute.h"
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#include "execute.h"
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#include "sprs.h"
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#include "sprs.h"
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#include "debug.h"
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#include "debug.h"
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|
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DECLARE_DEBUG_CHANNEL(jtag);
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|
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DevelopmentInterface development;
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DevelopmentInterface development;
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|
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/* External STALL signal to debug interface */
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/* External STALL signal to debug interface */
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int in_reset = 0;
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int in_reset = 0;
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|
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| Line 221... |
Line 221... |
static DebugScanChainIDs current_scan_chain = JTAG_CHAIN_GLOBAL;
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static DebugScanChainIDs current_scan_chain = JTAG_CHAIN_GLOBAL;
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|
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int DebugGetRegister(unsigned int address, unsigned long* data)
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int DebugGetRegister(unsigned int address, unsigned long* data)
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{
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{
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int err=0;
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int err=0;
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#ifdef DEBUG_JTAG
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TRACE_(jtag)("Debug get register %x\n",address);
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PRINTF("Debug get register %x\n",address);
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fflush(stdout);
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#endif
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switch(current_scan_chain)
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switch(current_scan_chain)
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{
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{
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case JTAG_CHAIN_DEBUG_UNIT:
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case JTAG_CHAIN_DEBUG_UNIT:
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*data = mfspr (address);
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*data = mfspr (address);
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debug (2, "READ (%08x) = %08x\n", address, *data);
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TRACE_(jtag)("READ (%08lx) = %08lx\n", address, *data);
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if (runtime.sim.fspr_log) {
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if (runtime.sim.fspr_log) {
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fprintf(runtime.sim.fspr_log, "Read from SPR : [%08X] -> [%08lX]\n",
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fprintf(runtime.sim.fspr_log, "Read from SPR : [%08X] -> [%08lX]\n",
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address, *data);
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address, *data);
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}
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}
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break;
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break;
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| Line 245... |
Line 242... |
break;
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break;
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case JTAG_CHAIN_WISHBONE:
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case JTAG_CHAIN_WISHBONE:
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err = debug_get_mem(address,data);
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err = debug_get_mem(address,data);
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break;
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break;
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}
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}
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#ifdef DEBUG_JTAG
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TRACE_(jtag)("!get reg %lx\n", *data);
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PRINTF("!get reg %x\n", *data);
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|
fflush(stdout);
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#endif
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return err;
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return err;
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}
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}
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|
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int DebugSetRegister(unsigned int address,unsigned long data)
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int DebugSetRegister(unsigned int address,unsigned long data)
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{
|
{
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int err=0;
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int err=0;
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#ifdef DEBUG_JTAG
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TRACE_(jtag)("Debug set register %x <- %lx\n", address, data);
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PRINTF("Debug set register %x <- %x\n", address, data);
|
|
fflush(stdout);
|
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#endif
|
|
switch(current_scan_chain)
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switch(current_scan_chain)
|
{
|
{
|
case JTAG_CHAIN_DEBUG_UNIT:
|
case JTAG_CHAIN_DEBUG_UNIT:
|
debug (2, "WRITE (%08x) = %08lx\n", address, data);
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TRACE_(jtag)("WRITE (%08x) = %08lx\n", address, data);
|
if (runtime.sim.fspr_log) {
|
if (runtime.sim.fspr_log) {
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fprintf(runtime.sim.fspr_log, "Write to SPR : [%08X] <- [%08lX]\n",
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fprintf(runtime.sim.fspr_log, "Write to SPR : [%08X] <- [%08lX]\n",
|
address, data);
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address, data);
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}
|
}
|
mtspr(address, data);
|
mtspr(address, data);
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| Line 279... |
Line 270... |
break;
|
break;
|
case JTAG_CHAIN_WISHBONE:
|
case JTAG_CHAIN_WISHBONE:
|
err = debug_set_mem (address, data);
|
err = debug_set_mem (address, data);
|
break;
|
break;
|
}
|
}
|
#ifdef DEBUG_JTAG
|
TRACE_(jtag)("!set reg\n");
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PRINTF("!set reg\n");
|
|
fflush(stdout);
|
|
#endif
|
|
return err;
|
return err;
|
}
|
}
|
|
|
int DebugSetChain(int chain)
|
int DebugSetChain(int chain)
|
{
|
{
|
#ifdef DEBUG_JTAG
|
TRACE_(jtag)("Debug set chain %x\n",chain);
|
PRINTF("Debug set chain %x\n",chain);
|
|
fflush(stdout);
|
|
#endif
|
|
switch(chain)
|
switch(chain)
|
{
|
{
|
case JTAG_CHAIN_DEBUG_UNIT:
|
case JTAG_CHAIN_DEBUG_UNIT:
|
case JTAG_CHAIN_TRACE:
|
case JTAG_CHAIN_TRACE:
|
case JTAG_CHAIN_DEVELOPMENT:
|
case JTAG_CHAIN_DEVELOPMENT:
|
| Line 304... |
Line 289... |
break;
|
break;
|
default: /* All other chains not implemented */
|
default: /* All other chains not implemented */
|
return JTAG_PROXY_INVALID_CHAIN;
|
return JTAG_PROXY_INVALID_CHAIN;
|
}
|
}
|
|
|
#ifdef DEBUG_JTAG
|
|
PRINTF("!set chain\n");
|
|
fflush(stdout);
|
|
#endif
|
|
return 0;
|
return 0;
|
}
|
}
|
|
|
void sim_reset ();
|
void sim_reset ();
|
|
|
| Line 350... |
Line 331... |
case DEVELOPINT_RECBP0: development.recbp = value; break;
|
case DEVELOPINT_RECBP0: development.recbp = value; break;
|
default:
|
default:
|
err = JTAG_PROXY_INVALID_ADDRESS;
|
err = JTAG_PROXY_INVALID_ADDRESS;
|
break;
|
break;
|
}
|
}
|
#ifdef DEBUG_JTAG
|
TRACE_(jtag)("set_devint_reg %08x = %08lx\n", address, data);
|
PRINTF("set_devint_reg %08x = %08x\n", address, data);
|
|
fflush(stdout);
|
|
#endif
|
|
return err;
|
return err;
|
}
|
}
|
|
|
/* Gets development interface register */
|
/* Gets development interface register */
|
int get_devint_reg(unsigned int address,unsigned long *data)
|
int get_devint_reg(unsigned int address,unsigned long *data)
|
| Line 384... |
Line 362... |
case DEVELOPINT_RECWP10: value = development.recwp[address - DEVELOPINT_RECWP0]; break;
|
case DEVELOPINT_RECWP10: value = development.recwp[address - DEVELOPINT_RECWP0]; break;
|
case DEVELOPINT_RECBP0: value = development.recbp; break;
|
case DEVELOPINT_RECBP0: value = development.recbp; break;
|
default: err = JTAG_PROXY_INVALID_ADDRESS; break;
|
default: err = JTAG_PROXY_INVALID_ADDRESS; break;
|
}
|
}
|
|
|
#ifdef DEBUG_JTAG
|
TRACE_(jtag)("get_devint_reg %08x = %08lx\n", address, value);
|
PRINTF("get_devint_reg %08x = %08x\n", address, value);
|
|
fflush(stdout);
|
|
#endif
|
|
*data = value;
|
*data = value;
|
return err;
|
return err;
|
}
|
}
|
|
|
/* Writes to bus address */
|
/* Writes to bus address */
|
int debug_set_mem (unsigned int address,unsigned long data)
|
int debug_set_mem (unsigned int address,unsigned long data)
|
{
|
{
|
int err = 0;
|
int err = 0;
|
debug (2, "MEMWRITE (%08x) = %08lx\n", address, data);
|
TRACE_(jtag)("MEMWRITE (%08x) = %08lx\n", address, data);
|
|
|
|
|
if(!verify_memoryarea(address))
|
if(!verify_memoryarea(address))
|
err = JTAG_PROXY_INVALID_ADDRESS;
|
err = JTAG_PROXY_INVALID_ADDRESS;
|
else {
|
else {
|
| Line 419... |
Line 394... |
err = JTAG_PROXY_INVALID_ADDRESS;
|
err = JTAG_PROXY_INVALID_ADDRESS;
|
else
|
else
|
{
|
{
|
*data=eval_direct32(address, 0, 0);
|
*data=eval_direct32(address, 0, 0);
|
}
|
}
|
debug (2, "MEMREAD (%08x) = %08lx\n", address, *data);
|
TRACE_(jtag)("MEMREAD (%08x) = %08lx\n", address, *data);
|
return err;
|
return err;
|
}
|
}
|
|
|
/* debug_ignore_exception returns 1 if the exception should be ignored. */
|
/* debug_ignore_exception returns 1 if the exception should be ignored. */
|
int debug_ignore_exception (unsigned long except)
|
int debug_ignore_exception (unsigned long except)
|
{
|
{
|
int result = 0;
|
int result = 0;
|
unsigned long dsr = cpu_state.sprs[SPR_DSR];
|
unsigned long dsr = cpu_state.sprs[SPR_DSR];
|
unsigned long drr = cpu_state.sprs[SPR_DRR];
|
unsigned long drr = cpu_state.sprs[SPR_DRR];
|
|
|
#if DEBUG_JTAG
|
|
PRINTF ("dsr 0x%08x drr 0x%08x \n", dsr, drr);
|
|
#endif
|
|
|
|
switch(except) {
|
switch(except) {
|
case EXCEPT_RESET: drr |= result = dsr & SPR_DSR_RSTE; break;
|
case EXCEPT_RESET: drr |= result = dsr & SPR_DSR_RSTE; break;
|
case EXCEPT_BUSERR: drr |= result = dsr & SPR_DSR_BUSEE; break;
|
case EXCEPT_BUSERR: drr |= result = dsr & SPR_DSR_BUSEE; break;
|
case EXCEPT_DPF: drr |= result = dsr & SPR_DSR_DPFE; break;
|
case EXCEPT_DPF: drr |= result = dsr & SPR_DSR_DPFE; break;
|
case EXCEPT_IPF: drr |= result = dsr & SPR_DSR_IPFE; break;
|
case EXCEPT_IPF: drr |= result = dsr & SPR_DSR_IPFE; break;
|
| Line 451... |
Line 422... |
case EXCEPT_SYSCALL: drr |= result = dsr & SPR_DSR_SCE; break;
|
case EXCEPT_SYSCALL: drr |= result = dsr & SPR_DSR_SCE; break;
|
case EXCEPT_TRAP: drr |= result = dsr & SPR_DSR_TE; break;
|
case EXCEPT_TRAP: drr |= result = dsr & SPR_DSR_TE; break;
|
default:
|
default:
|
break;
|
break;
|
}
|
}
|
#if DEBUG_JTAG
|
|
PRINTF ("dsr 0x%08x drr 0x%08x result %i\n", dsr, drr, result);
|
|
#endif
|
|
|
|
cpu_state.sprs[SPR_DRR] = drr;
|
cpu_state.sprs[SPR_DRR] = drr;
|
set_stall_state (result != 0);
|
set_stall_state (result != 0);
|
return (result != 0);
|
return (result != 0);
|
}
|
}
|
