URL https://opencores.org/ocsvn/or1k/or1k/trunk

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[/] [or1k/] [tags/] [stable_0_2_0_rc2/] [or1ksim/] [debug/] [debug_unit.c] - Diff between revs 1516 and 1537

Rev 1516	Rev 1537
Line 227...	Line 227...
`switch(current_scan_chain)`	`switch(current_scan_chain)`
`{`	`{`
`case JTAG_CHAIN_DEBUG_UNIT:`	`case JTAG_CHAIN_DEBUG_UNIT:`
`*data = mfspr(address);`	`*data = mfspr(address);`
`TRACE_(jtag)("READ (%08lx) = %08lx\n", address, *data);`	`TRACE_(jtag)("READ (%08lx) = %08lx\n", address, *data);`
`if (runtime.sim.fspr_log) {`
`fprintf(runtime.sim.fspr_log, "Read from SPR : [%08X] -> [%08lX]\n",`
`address, *data);`
`}`
`break;`	`break;`
`case JTAG_CHAIN_TRACE:`	`case JTAG_CHAIN_TRACE:`
`data = 0; / Scan chain not yet implemented */`	`data = 0; / Scan chain not yet implemented */`
`break;`	`break;`
`case JTAG_CHAIN_DEVELOPMENT:`	`case JTAG_CHAIN_DEVELOPMENT:`
Line 254...	Line 250...
`TRACE_(jtag)("Debug set register %x <- %lx\n", address, data);`	`TRACE_(jtag)("Debug set register %x <- %lx\n", address, data);`
`switch(current_scan_chain)`	`switch(current_scan_chain)`
`{`	`{`
`case JTAG_CHAIN_DEBUG_UNIT:`	`case JTAG_CHAIN_DEBUG_UNIT:`
`TRACE_(jtag)("WRITE (%08x) = %08lx\n", address, data);`	`TRACE_(jtag)("WRITE (%08x) = %08lx\n", address, data);`
`if (runtime.sim.fspr_log) {`
`fprintf(runtime.sim.fspr_log, "Write to SPR : [%08X] <- [%08lX]\n",`
`address, data);`
`}`
`mtspr(address, data);`	`mtspr(address, data);`
`break;`	`break;`
`case JTAG_CHAIN_TRACE:`	`case JTAG_CHAIN_TRACE:`
`err = JTAG_PROXY_ACCESS_EXCEPTION;`	`err = JTAG_PROXY_ACCESS_EXCEPTION;`
`break;`	`break;`