| Line 38... |
Line 38... |
#include "sim-config.h"
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#include "sim-config.h"
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#include "debug.h"
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#include "debug.h"
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DEFAULT_DEBUG_CHANNEL(immu);
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DEFAULT_DEBUG_CHANNEL(immu);
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extern int cont_run;
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/* Insn MMU */
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/* Insn MMU */
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static inline oraddr_t immu_simulate_tlb(oraddr_t virtaddr)
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static inline oraddr_t immu_simulate_tlb(oraddr_t virtaddr)
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{
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{
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int set, way = -1;
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int set, way = -1;
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int i;
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int i;
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oraddr_t tagaddr;
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oraddr_t tagaddr;
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oraddr_t vpn, ppn;
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oraddr_t vpn, ppn;
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if (!(mfspr(SPR_SR) & SPR_SR_IME) || !(testsprbits(SPR_UPR, SPR_UPR_IMP))) {
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if (!(cpu_state.sprs[SPR_SR] & SPR_SR_IME) ||
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!(cpu_state.sprs[SPR_UPR] & SPR_UPR_IMP)) {
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insn_ci = (virtaddr >= 0x80000000);
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insn_ci = (virtaddr >= 0x80000000);
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return virtaddr;
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return virtaddr;
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}
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}
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TRACE("IMMU enabled, checking mmu ways\n");
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TRACE("IMMU enabled, checking mmu ways\n");
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| Line 64... |
Line 63... |
vpn = virtaddr / (config.immu.pagesize * config.immu.nsets);
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vpn = virtaddr / (config.immu.pagesize * config.immu.nsets);
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/* Scan all ways and try to find a matching way. */
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/* Scan all ways and try to find a matching way. */
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for (i = 0; i < config.immu.nways; i++)
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for (i = 0; i < config.immu.nways; i++)
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if (((mfspr(SPR_ITLBMR_BASE(i) + set) / (config.immu.pagesize * config.immu.nsets)) == vpn) &&
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if (((mfspr(SPR_ITLBMR_BASE(i) + set) / (config.immu.pagesize * config.immu.nsets)) == vpn) &&
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testsprbits(SPR_ITLBMR_BASE(i) + set, SPR_ITLBMR_V))
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(cpu_state.sprs[SPR_ITLBMR_BASE(i) + set] & SPR_ITLBMR_V))
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way = i;
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way = i;
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/* Did we find our tlb entry? */
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/* Did we find our tlb entry? */
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if (way >= 0) { /* Yes, we did. */
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if (way >= 0) { /* Yes, we did. */
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immu_stats.fetch_tlbhit++;
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immu_stats.fetch_tlbhit++;
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TRACE("ITLB hit (virtaddr=%"PRIxADDR").\n", virtaddr);
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TRACE("ITLB hit (virtaddr=%"PRIxADDR").\n", virtaddr);
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/* Set LRUs */
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/* Set LRUs */
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for (i = 0; i < config.immu.nways; i++)
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for (i = 0; i < config.immu.nways; i++) {
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if (testsprbits(SPR_ITLBMR_BASE(i) + set, SPR_ITLBMR_LRU))
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uorreg_t lru = cpu_state.sprs[SPR_ITLBMR_BASE(i) + set];
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setsprbits(SPR_ITLBMR_BASE(i) + set, SPR_ITLBMR_LRU, getsprbits(SPR_ITLBMR_BASE(i) + set, SPR_ITLBMR_LRU) - 1);
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if (lru & SPR_ITLBMR_LRU) {
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setsprbits(SPR_ITLBMR_BASE(way) + set, SPR_ITLBMR_LRU, config.immu.nsets - 1);
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lru = (lru & ~SPR_ITLBMR_LRU) | ((lru & SPR_ITLBMR_LRU) - 0x40);
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cpu_state.sprs[SPR_ITLBMR_BASE(i) + set] = lru;
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}
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}
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cpu_state.sprs[SPR_ITLBMR_BASE(way) + set] &= ~SPR_ITLBMR_LRU;
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cpu_state.sprs[SPR_ITLBMR_BASE(way) + set] |= (config.immu.nsets - 1) << 6;
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/* Check if page is cache inhibited */
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/* Check if page is cache inhibited */
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insn_ci = (mfspr(SPR_ITLBTR_BASE(way) + set) & SPR_ITLBTR_CI) == SPR_ITLBTR_CI;
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insn_ci = (mfspr(SPR_ITLBTR_BASE(way) + set) & SPR_ITLBTR_CI) == SPR_ITLBTR_CI;
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runtime.sim.mem_cycles += config.immu.hitdelay;
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runtime.sim.mem_cycles += config.immu.hitdelay;
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Line 103... |
}
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}
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else { /* No, we didn't. */
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else { /* No, we didn't. */
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immu_stats.fetch_tlbmiss++;
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immu_stats.fetch_tlbmiss++;
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#if 0
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#if 0
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for (i = 0; i < config.immu.nways; i++)
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for (i = 0; i < config.immu.nways; i++)
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if (getsprbits(SPR_ITLBMR_BASE(i) + set, SPR_ITLBMR_LRU) < minlru)
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if (((cpu_state.sprs[SPR_ITLBMR_BASE(i) + set] & SPR_ITLBMR_LRU) >> 6) < minlru)
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minway = i;
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minway = i;
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setsprbits(SPR_ITLBMR_BASE(minway) + set, SPR_ITLBMR_VPN, vpn);
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cpu_state.sprs[SPR_ITLBMR_BASE(minway) + set] &= ~SPR_ITLBMR_VPN;
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for (i = 0; i < config.immu.nways; i++)
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cpu_state.sprs[SPR_ITLBMR_BASE(minway) + set] |= vpn << 12;
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if (testsprbits(SPR_ITLBMR_BASE(i) + set, SPR_ITLBMR_LRU))
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for (i = 0; i < config.immu.nways; i++) {
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setsprbits(SPR_ITLBMR_BASE(i) + set, SPR_ITLBMR_LRU, getsprbits(SPR_ITLBMR_BASE(i) + set, SPR_ITLBMR_LRU) - 1);
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uorreg_t lru = cpu_state.sprs[SPR_ITLBMR_BASE(i) + set];
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setsprbits(SPR_ITLBMR_BASE(minway) + set, SPR_ITLBMR_LRU, config.immu.ustates - 1);
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if (lru & SPR_ITLBMR_LRU) {
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setsprbits(SPR_ITLBTR_BASE(minway) + set, SPR_ITLBTR_PPN, vpn); /* 1 to 1 */
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lru = (lru & ~SPR_ITLBMR_LRU) | ((lru & SPR_ITLBMR_LRU) - 0x40);
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setsprbits(SPR_ITLBMR_BASE(minway) + set, SPR_ITLBMR_V, 1);
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cpu_state.sprs[SPR_ITLBMR_BASE(i) + set] = lru;
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}
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}
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cpu_state.sprs[SPR_ITLBMR_BASE(way) + set] &= ~SPR_ITLBMR_LRU;
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cpu_state.sprs[SPR_ITLBMR_BASE(way) + set] |= (config.immu.nsets - 1) << 6;
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/* 1 to 1 mapping */
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cpu_state.sprs[SPR_ITLBTR_BASE(minway) + set] &= ~SPR_ITLBTR_PPN;
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cpu_state.sprs[SPR_ITLBTR_BASE(minway) + set] |= vpn << 12;
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cpu_state.sprs[SPR_ITLBMR_BASE(minway) + set] |= SPR_ITLBMR_V;
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#endif
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#endif
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/* if tlb refill implemented in HW */
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/* if tlb refill implemented in HW */
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/* return getsprbits(SPR_ITLBTR_BASE(minway) + set, SPR_ITLBTR_PPN) * config.immu.pagesize + (virtaddr % config.immu.pagesize); */
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/* return ((cpu_state.sprs[SPR_ITLBTR_BASE(minway) + set] & SPR_ITLBTR_PPN) >> 12) * config.immu.pagesize + (virtaddr % config.immu.pagesize); */
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runtime.sim.mem_cycles += config.immu.missdelay;
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runtime.sim.mem_cycles += config.immu.missdelay;
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except_handle(EXCEPT_ITLBMISS, virtaddr);
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except_handle(EXCEPT_ITLBMISS, virtaddr);
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return 0;
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return 0;
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}
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}
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| Line 137... |
Line 151... |
int set, way = -1;
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int set, way = -1;
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int i;
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int i;
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oraddr_t tagaddr;
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oraddr_t tagaddr;
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oraddr_t vpn, ppn;
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oraddr_t vpn, ppn;
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if (!(mfspr(SPR_SR) & SPR_SR_IME) || !(testsprbits(SPR_UPR, SPR_UPR_IMP))) {
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if (!(cpu_state.sprs[SPR_SR] & SPR_SR_IME) ||
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!(cpu_state.sprs[SPR_UPR] & SPR_UPR_IMP)) {
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return(virtaddr);
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return(virtaddr);
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}
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}
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/* Which set to check out? */
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/* Which set to check out? */
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set = (virtaddr / config.immu.pagesize) % config.immu.nsets;
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set = (virtaddr / config.immu.pagesize) % config.immu.nsets;
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| Line 149... |
Line 164... |
vpn = virtaddr / (config.immu.pagesize * config.immu.nsets);
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vpn = virtaddr / (config.immu.pagesize * config.immu.nsets);
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/* Scan all ways and try to find a matching way. */
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/* Scan all ways and try to find a matching way. */
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for (i = 0; i < config.immu.nways; i++)
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for (i = 0; i < config.immu.nways; i++)
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if (((mfspr(SPR_ITLBMR_BASE(i) + set) / (config.immu.pagesize * config.immu.nsets)) == vpn) &&
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if (((mfspr(SPR_ITLBMR_BASE(i) + set) / (config.immu.pagesize * config.immu.nsets)) == vpn) &&
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testsprbits(SPR_ITLBMR_BASE(i) + set, SPR_ITLBMR_V))
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(cpu_state.sprs[SPR_ITLBMR_BASE(i) + set] & SPR_ITLBMR_V))
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way = i;
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way = i;
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/* Did we find our tlb entry? */
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/* Did we find our tlb entry? */
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if (way >= 0) { /* Yes, we did. */
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if (way >= 0) { /* Yes, we did. */
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| Line 188... |
Line 203... |
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/* PRINTF("IMMU translate(%x) = %x\n", virtaddr, phyaddr);*/
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/* PRINTF("IMMU translate(%x) = %x\n", virtaddr, phyaddr);*/
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return phyaddr;
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return phyaddr;
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}
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}
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void itlb_info()
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void itlb_info(void)
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{
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{
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if (!testsprbits(SPR_UPR, SPR_UPR_IMP)) {
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if (!(cpu_state.sprs[SPR_UPR] & SPR_UPR_IMP)) {
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PRINTF("IMMU not implemented. Set UPR[IMP].\n");
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PRINTF("IMMU not implemented. Set UPR[IMP].\n");
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return;
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return;
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}
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}
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PRINTF("Insn MMU %dKB: ", config.immu.nsets * config.immu.entrysize * config.immu.nways / 1024);
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PRINTF("Insn MMU %dKB: ", config.immu.nsets * config.immu.entrysize * config.immu.nways / 1024);
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| Line 218... |
Line 233... |
{
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{
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int set;
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int set;
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int way;
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int way;
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int end_set = config.immu.nsets;
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int end_set = config.immu.nsets;
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if (!testsprbits(SPR_UPR, SPR_UPR_IMP)) {
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if (!(cpu_state.sprs[SPR_UPR] & SPR_UPR_IMP)) {
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PRINTF("IMMU not implemented. Set UPR[IMP].\n");
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PRINTF("IMMU not implemented. Set UPR[IMP].\n");
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return;
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return;
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}
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}
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if ((start_set >= 0) && (start_set < end_set))
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if ((start_set >= 0) && (start_set < end_set))
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| Line 252... |
Line 267... |
}
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}
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/*---------------------------------------------------[ IMMU configuration ]---*/
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/*---------------------------------------------------[ IMMU configuration ]---*/
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void immu_enabled(union param_val val, void *dat)
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void immu_enabled(union param_val val, void *dat)
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{
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{
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setsprbits (SPR_UPR, SPR_UPR_IMP, val.int_val ? 1 : 0);
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if(val.int_val)
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cpu_state.sprs[SPR_UPR] |= SPR_UPR_IMP;
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else
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cpu_state.sprs[SPR_UPR] &= ~SPR_UPR_IMP;
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config.immu.enabled = val.int_val;
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config.immu.enabled = val.int_val;
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}
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}
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void immu_nsets(union param_val val, void *dat)
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void immu_nsets(union param_val val, void *dat)
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{
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{
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if (is_power2(val.int_val) && val.int_val <= 256) {
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if (is_power2(val.int_val) && val.int_val <= 256) {
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config.immu.nsets = val.int_val;
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config.immu.nsets = val.int_val;
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setsprbits (SPR_IMMUCFGR, SPR_IMMUCFGR_NTS, log2(val.int_val));
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cpu_state.sprs[SPR_IMMUCFGR] &= ~SPR_IMMUCFGR_NTS;
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cpu_state.sprs[SPR_IMMUCFGR] |= log2(val.int_val) << 3;
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}
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}
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else
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else
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CONFIG_ERROR("value of power of two and lower or equal than 256 expected.");
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CONFIG_ERROR("value of power of two and lower or equal than 256 expected.");
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}
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}
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void immu_nways(union param_val val, void *dat)
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void immu_nways(union param_val val, void *dat)
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{
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{
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if (val.int_val >= 1 && val.int_val <= 4) {
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if (val.int_val >= 1 && val.int_val <= 4) {
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config.immu.nways = val.int_val;
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config.immu.nways = val.int_val;
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setsprbits (SPR_DMMUCFGR, SPR_DMMUCFGR_NTW, val.int_val-1);
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cpu_state.sprs[SPR_IMMUCFGR] &= ~SPR_IMMUCFGR_NTW;
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cpu_state.sprs[SPR_IMMUCFGR] |= val.int_val - 1;
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}
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}
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else
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else
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CONFIG_ERROR("value 1, 2, 3 or 4 expected.");
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CONFIG_ERROR("value 1, 2, 3 or 4 expected.");
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}
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}
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