| Line 22... |
Line 22... |
* This simulation of the DMA core is not meant to be full.
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* This simulation of the DMA core is not meant to be full.
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* It is written only to allow simulating the Ethernet core.
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* It is written only to allow simulating the Ethernet core.
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* Of course, if anyone feels like perfecting it, feel free...
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* Of course, if anyone feels like perfecting it, feel free...
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*/
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*/
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#include <string.h>
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#include "dma.h"
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#include "dma.h"
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#include "sim-config.h"
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#include "sim-config.h"
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#include "pic.h"
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#include "pic.h"
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#include "abstract.h"
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#include "abstract.h"
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#include "fields.h"
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#include "fields.h"
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#include "debug.h"
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/* The representation of the DMA controllers */
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/* The representation of the DMA controllers */
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static struct dma_controller dmas[MAX_DMAS];
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static struct dma_controller dmas[MAX_DMAS];
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static unsigned long dma_read32( unsigned long addr );
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static unsigned long dma_read32( unsigned long addr );
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| Line 81... |
Line 84... |
struct dma_controller *dma = &(dmas[i]);
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struct dma_controller *dma = &(dmas[i]);
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if ( dma->baseaddr == 0 )
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if ( dma->baseaddr == 0 )
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continue;
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continue;
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PRINTF( "\nDMA controller %u at 0x%08X:\n", i, dma->baseaddr );
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PRINTF( "\nDMA controller %u at 0x%08lX:\n", i, dma->baseaddr );
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PRINTF( "CSR : 0x%08lX\n", dma->regs.csr );
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PRINTF( "CSR : 0x%08lX\n", dma->regs.csr );
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PRINTF( "INT_MSK_A : 0x%08lX\n", dma->regs.int_msk_a );
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PRINTF( "INT_MSK_A : 0x%08lX\n", dma->regs.int_msk_a );
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PRINTF( "INT_MSK_B : 0x%08lX\n", dma->regs.int_msk_b );
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PRINTF( "INT_MSK_B : 0x%08lX\n", dma->regs.int_msk_b );
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PRINTF( "INT_SRC_A : 0x%08lX\n", dma->regs.int_src_a );
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PRINTF( "INT_SRC_A : 0x%08lX\n", dma->regs.int_src_a );
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PRINTF( "INT_SRC_B : 0x%08lX\n", dma->regs.int_src_b );
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PRINTF( "INT_SRC_B : 0x%08lX\n", dma->regs.int_src_b );
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| Line 302... |
Line 305... |
* This does the actual "DMA" operation.
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* This does the actual "DMA" operation.
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* One chunk is transferred per clock.
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* One chunk is transferred per clock.
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*/
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*/
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void dma_controller_clock( struct dma_controller *dma )
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void dma_controller_clock( struct dma_controller *dma )
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{
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{
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unsigned chno, i;
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unsigned chno;
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int breakpoint = 0;
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int breakpoint = 0;
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for ( chno = 0; chno < DMA_NUM_CHANNELS; ++ chno ) {
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for ( chno = 0; chno < DMA_NUM_CHANNELS; ++ chno ) {
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struct dma_channel *channel = &(dma->ch[chno]);
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struct dma_channel *channel = &(dma->ch[chno]);
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| Line 444... |
Line 447... |
}
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}
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/* If needed, write amount of data transferred back to memory */
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/* If needed, write amount of data transferred back to memory */
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if ( TEST_FLAG( channel->regs.csr, DMA_CH_CSR, SZ_WB ) &&
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if ( TEST_FLAG( channel->regs.csr, DMA_CH_CSR, SZ_WB ) &&
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TEST_FLAG( channel->regs.csr, DMA_CH_CSR, USE_ED ) ) {
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TEST_FLAG( channel->regs.csr, DMA_CH_CSR, USE_ED ) ) {
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int breakpoint = 0;
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unsigned long desc_csr = eval_mem32( channel->regs.desc + DMA_DESC_CSR, &breakpoint );
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/* TODO: What should we write back? Doc says "total number of remaining bytes" !? */
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/* TODO: What should we write back? Doc says "total number of remaining bytes" !? */
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unsigned long remaining_words = channel->total_size - channel->words_transferred;
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unsigned long remaining_words = channel->total_size - channel->words_transferred;
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SET_FIELD( channel->regs.sz, DMA_DESC_CSR, TOT_SZ, remaining_words );
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SET_FIELD( channel->regs.sz, DMA_DESC_CSR, TOT_SZ, remaining_words );
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}
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}
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