| Line 237... |
Line 237... |
void dma_write_ch_csr( struct dma_channel *channel, unsigned long value )
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void dma_write_ch_csr( struct dma_channel *channel, unsigned long value )
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{
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{
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/* Check if we should *start* a transfer */
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/* Check if we should *start* a transfer */
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if ( !TEST_FLAG( channel->regs.csr, DMA_CH_CSR, CH_EN ) &&
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if ( !TEST_FLAG( channel->regs.csr, DMA_CH_CSR, CH_EN ) &&
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TEST_FLAG( value, DMA_CH_CSR, CH_EN ))
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TEST_FLAG( value, DMA_CH_CSR, CH_EN ))
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SCHED_ADD( dma_channel_clock, channel, runtime.sim.cycles + 1 );
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SCHED_ADD( dma_channel_clock, channel, 1 );
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else if ( !TEST_FLAG( value, DMA_CH_CSR, CH_EN ) )
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else if ( !TEST_FLAG( value, DMA_CH_CSR, CH_EN ) )
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/* The CH_EN flag is clear, check if we have a transfer in progress and
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/* The CH_EN flag is clear, check if we have a transfer in progress and
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* clear it */
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* clear it */
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SCHED_FIND_REMOVE( dma_channel_clock, channel );
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SCHED_FIND_REMOVE( dma_channel_clock, channel );
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|
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| Line 279... |
Line 279... |
}
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}
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|
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/* In HW Handshake mode, only work when dma_req_i asserted */
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/* In HW Handshake mode, only work when dma_req_i asserted */
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if ( TEST_FLAG(channel->regs.csr, DMA_CH_CSR, MODE) && !channel->dma_req_i ) {
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if ( TEST_FLAG(channel->regs.csr, DMA_CH_CSR, MODE) && !channel->dma_req_i ) {
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/* Reschedule */
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/* Reschedule */
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SCHED_ADD( dma_channel_clock, dat, runtime.sim.cycles + 1 );
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SCHED_ADD( dma_channel_clock, dat, 1 );
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return;
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return;
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}
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}
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/* If this is the first cycle of the transfer, initialize our state */
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/* If this is the first cycle of the transfer, initialize our state */
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if ( !TEST_FLAG( channel->regs.csr, DMA_CH_CSR, BUSY ) ) {
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if ( !TEST_FLAG( channel->regs.csr, DMA_CH_CSR, BUSY ) ) {
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| Line 333... |
Line 333... |
dma_channel_terminate_transfer( channel, 1 );
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dma_channel_terminate_transfer( channel, 1 );
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return;
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return;
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}
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}
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/* Reschedule to transfer the next chunk */
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/* Reschedule to transfer the next chunk */
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SCHED_ADD( dma_channel_clock, dat, runtime.sim.cycles + 1 );
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SCHED_ADD( dma_channel_clock, dat, 1 );
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}
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}
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/* Copy relevant valued from linked list descriptor to channel registers */
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/* Copy relevant valued from linked list descriptor to channel registers */
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void dma_load_descriptor( struct dma_channel *channel )
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void dma_load_descriptor( struct dma_channel *channel )
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| Line 385... |
Line 385... |
/* Might be working in a linked list */
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/* Might be working in a linked list */
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if ( channel->load_next_descriptor_when_done ) {
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if ( channel->load_next_descriptor_when_done ) {
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dma_load_descriptor( channel );
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dma_load_descriptor( channel );
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dma_init_transfer( channel );
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dma_init_transfer( channel );
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/* Reschedule */
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/* Reschedule */
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SCHED_ADD( dma_channel_clock, channel, runtime.sim.cycles + 1 );
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SCHED_ADD( dma_channel_clock, channel, 1 );
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return;
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return;
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}
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}
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/* Might be in auto-restart mode */
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/* Might be in auto-restart mode */
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if ( TEST_FLAG( channel->regs.csr, DMA_CH_CSR, ARS ) ) {
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if ( TEST_FLAG( channel->regs.csr, DMA_CH_CSR, ARS ) ) {
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