| Line 61... |
Line 61... |
/* Write a register */
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/* Write a register */
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void fb_write32 (oraddr_t addr, uint32_t value, void *dat)
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void fb_write32 (oraddr_t addr, uint32_t value, void *dat)
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{
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{
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struct fb_state *fb = dat;
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struct fb_state *fb = dat;
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|
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oraddr_t a = (addr - fb->baseaddr);
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switch (addr) {
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|
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switch (a) {
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case FB_CTRL: fb->ctrl = value; break;
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case FB_CTRL: fb->ctrl = value; break;
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case FB_BUFADDR: change_buf_addr (fb, value); break;
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case FB_BUFADDR: change_buf_addr (fb, value); break;
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case FB_CAMBUFADDR: fb->cam_addr = value; break;
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case FB_CAMBUFADDR: fb->cam_addr = value; break;
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case FB_CAMPOSADDR: fb->camera_pos = value;
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case FB_CAMPOSADDR: fb->camera_pos = value;
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fb->camerax = value % FB_SIZEX;
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fb->camerax = value % FB_SIZEX;
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fb->cameray = value / FB_SIZEX;
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fb->cameray = value / FB_SIZEX;
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break;
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break;
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default:
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default:
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a -= FB_PAL;
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addr -= FB_PAL;
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a /= 4;
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addr /= 4;
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if (a < 0 || a >= 256) {
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if (addr < 0 || addr >= 256) {
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fprintf (stderr, "Write out of palette buffer (0x%"PRIxADDR")!\n", addr);
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fprintf (stderr, "Write out of palette buffer (0x%"PRIxADDR")!\n", addr);
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} else fb->pal[a] = value;
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} else fb->pal[addr] = value;
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break;
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break;
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}
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}
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}
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}
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|
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/* Read a register */
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/* Read a register */
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oraddr_t fb_read32 (oraddr_t addr, void *dat)
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oraddr_t fb_read32 (oraddr_t addr, void *dat)
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{
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{
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struct fb_state *fb = dat;
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struct fb_state *fb = dat;
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|
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oraddr_t a = (addr - fb->baseaddr);
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switch (addr) {
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|
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switch (a) {
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case FB_CTRL:
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case FB_CTRL:
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return fb->ctrl & ~0xff000000| (fb->in_refresh ? 0x80000000 : 0) | ((unsigned long)(fb->refresh_count & 0x7f) << 24);
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return fb->ctrl & ~0xff000000| (fb->in_refresh ? 0x80000000 : 0) | ((unsigned long)(fb->refresh_count & 0x7f) << 24);
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break;
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break;
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case FB_BUFADDR: return fb->addr; break;
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case FB_BUFADDR: return fb->addr; break;
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case FB_CAMBUFADDR: return fb->cam_addr; break;
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case FB_CAMBUFADDR: return fb->cam_addr; break;
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case FB_CAMPOSADDR: return fb->camera_pos; break;
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case FB_CAMPOSADDR: return fb->camera_pos; break;
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default:
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default:
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a -= FB_PAL;
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addr -= FB_PAL;
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a /= 4;
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addr /= 4;
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if (a < 0 || a >= 256) {
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if (addr < 0 || addr >= 256) {
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fprintf (stderr, "Read out of palette buffer (0x%"PRIxADDR")!\n", addr);
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fprintf (stderr, "Read out of palette buffer (0x%"PRIxADDR")!\n", addr);
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return 0;
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return 0;
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} else return fb->pal[a];
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} else return fb->pal[addr];
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}
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}
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}
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}
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|
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/* define these also for big endian */
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/* define these also for big endian */
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#if __BIG_ENDIAN__
|
#if __BIG_ENDIAN__
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| Line 366... |
Line 362... |
}
|
}
|
|
|
void fb_sec_end(void *dat)
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void fb_sec_end(void *dat)
|
{
|
{
|
struct fb_state *fb = dat;
|
struct fb_state *fb = dat;
|
|
struct mem_ops ops;
|
|
|
if(!fb->enabled) {
|
if(!fb->enabled) {
|
free(dat);
|
free(dat);
|
return;
|
return;
|
}
|
}
|
|
|
if (fb->baseaddr)
|
memset(&ops, 0, sizeof(struct mem_ops));
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register_memoryarea(fb->baseaddr, FB_PAL + 256*4, 4, 0, fb_read32, fb_write32, dat);
|
|
|
ops.readfunc32 = fb_read32;
|
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ops.writefunc32 = fb_write32;
|
|
ops.write_dat32 = dat;
|
|
ops.read_dat32 = dat;
|
|
|
|
/* FIXME: Correct delay? */
|
|
ops.delayr = 2;
|
|
ops.delayw = 2;
|
|
|
|
reg_mem_area(fb->baseaddr, FB_PAL + 256*4, 0, &ops);
|
|
|
reg_sim_reset(fb_reset, dat);
|
reg_sim_reset(fb_reset, dat);
|
}
|
}
|
|
|
void reg_fb_sec(void)
|
void reg_fb_sec(void)
|
