URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [stable_0_2_0_rc2/] [or1ksim/] [peripheral/] [mc.c] - Diff between revs 1308 and 1350

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 1308	Rev 1350
Line 28...	Line 28...
`- memory refresh is not simulated`	`- memory refresh is not simulated`
`*/`	`*/`

`#include <string.h>`	`#include <string.h>`

	`#include "config.h"`

	`#ifdef HAVE_INTTYPES_H`
	`#include <inttypes.h>`
	`#endif`

	`#include "port.h"`
	`#include "arch.h"`
`#include "mc.h"`	`#include "mc.h"`
`#include "abstract.h"`	`#include "abstract.h"`
`#include "sim-config.h"`	`#include "sim-config.h"`
`#include "debug.h"`	`#include "debug.h"`

Line 66...	Line 74...
`mem_dev = mem_dev->next;`	`mem_dev = mem_dev->next;`
`}`	`}`
`}`	`}`

`/* Set a specific MC register with value. */`	`/* Set a specific MC register with value. */`
`void mc_write_word(unsigned long addr, unsigned long value)`	`void mc_write_word(oraddr_t addr, uint32_t value)`
`{`	`{`
`int chipsel;`	`int chipsel;`

`debug(5, "mc_write_word(%x,%08x)\n", addr, (unsigned)value);`	`debug(5, "mc_write_word(%"PRIxADDR",%08"PRIx32")\n", addr, value);`

`addr -= config.mc.baseaddr;`	`addr -= config.mc.baseaddr;`

`switch (addr) {`	`switch (addr) {`
`case MC_CSR:`	`case MC_CSR:`
Line 97...	Line 105...
`mc.csc[addr >> 3] = value;`	`mc.csc[addr >> 3] = value;`

`set_csc_tms (addr >> 3, mc.csc[addr >> 3], mc.tms[addr >> 3]);`	`set_csc_tms (addr >> 3, mc.csc[addr >> 3], mc.tms[addr >> 3]);`
`break;`	`break;`
`} else`	`} else`
`debug(1, "write out of range (addr %x)\n", addr + config.mc.baseaddr);`	`debug(1, "write out of range (addr %"PRIxADDR")\n", addr + config.mc.baseaddr);`
`}`	`}`
`}`	`}`

`/* Read a specific MC register. */`	`/* Read a specific MC register. */`
`unsigned long mc_read_word(unsigned long addr)`	`uint32_t mc_read_word(oraddr_t addr)`
`{`	`{`
`unsigned long value = 0;`	`uint32_t value = 0;`

`debug(5, "mc_read_word(%x)", addr);`	`debug(5, "mc_read_word(%"PRIxADDR")", addr);`

`addr -= config.mc.baseaddr;`	`addr -= config.mc.baseaddr;`

`switch (addr) {`	`switch (addr) {`
`case MC_CSR:`	`case MC_CSR:`
Line 128...	Line 136...
`if ((addr >> 2) & 1)`	`if ((addr >> 2) & 1)`
`value = mc.tms[addr >> 3];`	`value = mc.tms[addr >> 3];`
`else`	`else`
`value = mc.csc[addr >> 3];`	`value = mc.csc[addr >> 3];`
`} else`	`} else`
`debug(1, " read out of range (addr %x)\n", addr + config.mc.baseaddr);`	`debug(1, " read out of range (addr %"PRIxADDR")\n", addr + config.mc.baseaddr);`
`break;`	`break;`
`}`	`}`
`debug(5, " value(%x)\n", value);`	`debug(5, " value(%"PRIx32")\n", value);`
`return value;`	`return value;`
`}`	`}`

`/* Read POC register and init memory controler regs. */`	`/* Read POC register and init memory controler regs. */`
`void mc_reset()`	`void mc_reset()`
Line 178...	Line 186...

`void mc_status()`	`void mc_status()`
`{`	`{`
`int i;`	`int i;`

`PRINTF( "\nMemory Controller at 0x%08lX:\n", config.mc.baseaddr );`	`PRINTF( "\nMemory Controller at 0x%lX:\n", config.mc.baseaddr );`
`PRINTF( "POC: 0x%08lX\n", mc.poc );`	`PRINTF( "POC: 0x%08lX\n", mc.poc );`
`PRINTF( "BAS: 0x%08lX\n", mc.ba_mask );`	`PRINTF( "BAS: 0x%08lX\n", mc.ba_mask );`
`PRINTF( "CSR: 0x%08lX\n", mc.csr );`	`PRINTF( "CSR: 0x%08lX\n", mc.csr );`

`for (i=0; i<N_CE; i++) {`	`for (i=0; i<N_CE; i++) {`

Browse

Tools

Subversion Repositories or1k

[/] [or1k/] [tags/] [stable_0_2_0_rc2/] [or1ksim/] [peripheral/] [mc.c] - Diff between revs 1308 and 1350