| Line 39... |
Line 39... |
void set_csc_tms (int cs, unsigned long csc, unsigned long tms) {
|
void set_csc_tms (int cs, unsigned long csc, unsigned long tms) {
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struct dev_memarea *mem_dev = dev_list;
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struct dev_memarea *mem_dev = dev_list;
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|
|
while (mem_dev) {
|
while (mem_dev) {
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if (mem_dev->chip_select == cs) {
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if (mem_dev->chip_select == cs) {
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printf("CS0 addr_mask = %.8lx addr_compare = %.8lx\n", mem_dev->addr_mask, mem_dev->addr_compare);
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mem_dev->addr_mask = 0xe0000000 | mc.ba_mask << 21;
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mem_dev->addr_mask = mc.ba_mask << 21;
|
|
mem_dev->addr_compare = ((csc >> MC_CSC_SEL_OFFSET) & 0xff) << 21;
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mem_dev->addr_compare = ((csc >> MC_CSC_SEL_OFFSET) & 0xff) << 21;
|
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mem_dev->valid = (csc >> MC_CSC_EN_OFFSET) & 0x01;
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|
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if ((csc >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_ASYNC) {
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if ((csc >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_ASYNC) {
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mem_dev->delayr = (tms & 0xff) + ((tms >> 8) & 0x0f);
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mem_dev->delayr = (tms & 0xff) + ((tms >> 8) & 0x0f);
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mem_dev->delayw = ((tms >> 12) & 0x0f) + ((tms >> 16) & 0x0f) + ((tms >> 20) & 0x3f);
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mem_dev->delayw = ((tms >> 12) & 0x0f) + ((tms >> 16) & 0x0f) + ((tms >> 20) & 0x3f);
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} else if ((csc >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_SDRAM) {
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} else if ((csc >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_SDRAM) {
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| Line 56... |
Line 56... |
mem_dev->delayw = 2;
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mem_dev->delayw = 2;
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} else if ((csc >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_SYNC) {
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} else if ((csc >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_SYNC) {
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mem_dev->delayr = 2;
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mem_dev->delayr = 2;
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mem_dev->delayw = 2;
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mem_dev->delayw = 2;
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}
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}
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break;
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return;
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}
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}
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mem_dev = mem_dev->next;
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mem_dev = mem_dev->next;
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}
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}
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}
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}
|
|
|
| Line 80... |
Line 80... |
case MC_POC:
|
case MC_POC:
|
fprintf (stderr, "warning: write to MC's POC register!");
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fprintf (stderr, "warning: write to MC's POC register!");
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break;
|
break;
|
case MC_BA_MASK:
|
case MC_BA_MASK:
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mc.ba_mask = value & MC_BA_MASK_VALID;
|
mc.ba_mask = value & MC_BA_MASK_VALID;
|
|
for (chipsel = 0; chipsel < N_CE; chipsel++)
|
|
set_csc_tms (chipsel, mc.csc[chipsel], mc.tms[chipsel]);
|
break;
|
break;
|
default:
|
default:
|
if (addr >= MC_CSC(0) && addr <= MC_TMS(N_CE - 1)) {
|
if (addr >= MC_CSC(0) && addr <= MC_TMS(N_CE - 1)) {
|
addr -= MC_CSC(0);
|
addr -= MC_CSC(0);
|
if ((addr >> 2) & 1)
|
if ((addr >> 2) & 1)
|
| Line 133... |
Line 135... |
}
|
}
|
|
|
/* Read POC register and init memory controler regs. */
|
/* Read POC register and init memory controler regs. */
|
void mc_reset()
|
void mc_reset()
|
{
|
{
|
|
struct dev_memarea *mem_dev = dev_list;
|
|
|
if (config.mc.enabled) {
|
if (config.mc.enabled) {
|
printf("Resetting memory controller.\n");
|
printf("Resetting memory controller.\n");
|
memset(&mc, 0, sizeof(struct mc));
|
memset(&mc, 0, sizeof(struct mc));
|
|
|
mc.poc = config.mc.POC;
|
mc.poc = config.mc.POC;
|
| Line 152... |
Line 156... |
mc.tms[0] = MC_TMS_SSRAM_VALID;
|
mc.tms[0] = MC_TMS_SSRAM_VALID;
|
} else if ((mc.csc[0] >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_SYNC) {
|
} else if ((mc.csc[0] >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_SYNC) {
|
mc.tms[0] = MC_TMS_SYNC_VALID;
|
mc.tms[0] = MC_TMS_SYNC_VALID;
|
}
|
}
|
|
|
|
while (mem_dev) {
|
|
mem_dev->valid = 0;
|
|
mem_dev = mem_dev->next;
|
|
}
|
|
|
set_csc_tms (0, mc.csc[0], mc.tms[0]);
|
set_csc_tms (0, mc.csc[0], mc.tms[0]);
|
|
|
register_memoryarea(config.mc.baseaddr, MC_ADDR_SPACE, 4, mc_read_word, mc_write_word);
|
register_memoryarea(config.mc.baseaddr, MC_ADDR_SPACE, 4, mc_read_word, mc_write_word);
|
}
|
}
|
}
|
}
|
