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Line 38... |
#include "opcode/or32.h"
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#include "opcode/or32.h"
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#include "spr_defs.h"
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#include "spr_defs.h"
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#include "execute.h"
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#include "execute.h"
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#include "except.h"
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#include "except.h"
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#include "sprs.h"
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#include "sprs.h"
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#include "sim-config.h"
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#include "sched.h"
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#include "sched.h"
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#include "debug.h"
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#include "debug.h"
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DEFAULT_DEBUG_CHANNEL(pic);
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DEFAULT_DEBUG_CHANNEL(pic);
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/* Reset. It initializes PIC registers. */
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/* Reset. It initializes PIC registers. */
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void pic_reset()
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void pic_reset()
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{
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{
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PRINTF("Resetting PIC.\n");
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PRINTF("Resetting PIC.\n");
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mtspr(SPR_PICMR, 0);
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cpu_state.sprs[SPR_PICMR] = 0;
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mtspr(SPR_PICPR, 0);
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cpu_state.sprs[SPR_PICPR] = 0;
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mtspr(SPR_PICSR, 0);
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cpu_state.sprs[SPR_PICSR] = 0;
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}
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}
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/* Handles the reporting of an interrupt if it had to be delayed */
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/* Handles the reporting of an interrupt if it had to be delayed */
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void pic_clock(void *dat)
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void pic_clock(void *dat)
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{
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{
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/* Don't do anything if interrupts not currently enabled */
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/* Don't do anything if interrupts not currently enabled */
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if(testsprbits (SPR_SR, SPR_SR_IEE)) {
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if(cpu_state.sprs[SPR_SR] & SPR_SR_IEE) {
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TRACE("Delivering interrupt on cycle %lli\n", runtime.sim.cycles);
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TRACE("Delivering interrupt on cycle %lli\n", runtime.sim.cycles);
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except_handle(EXCEPT_INT, mfspr(SPR_EEAR_BASE));
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except_handle(EXCEPT_INT, cpu_state.sprs[SPR_EEAR_BASE]);
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} else if(testsprbits (SPR_PICSR, (int)dat))
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} else if(cpu_state.sprs[SPR_PICSR] & (1 << (int)dat))
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/* Reschedule only if the interrupt hasn't been cleared */
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/* Reschedule only if the interrupt hasn't been cleared */
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SCHED_ADD(pic_clock, dat, 1);
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SCHED_ADD(pic_clock, dat, 1);
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}
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}
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/* WARNING: Don't eaven try and call this function *during* a simulated
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/* WARNING: Don't eaven try and call this function *during* a simulated
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Line 73... |
/* WARNING2: Don't except report_interrupt to return! However, it also _may_
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/* WARNING2: Don't except report_interrupt to return! However, it also _may_
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* return. Make sure you handle this case aswell. */
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* return. Make sure you handle this case aswell. */
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/* Asserts interrupt to the PIC. */
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/* Asserts interrupt to the PIC. */
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void report_interrupt(int line)
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void report_interrupt(int line)
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{
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{
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setsprbits(SPR_PMR, SPR_PMR_DME, 0); /* Disable doze mode */
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/* Disable doze and sleep mode */
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setsprbits(SPR_PMR, SPR_PMR_SME, 0); /* Disable sleep mode */
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cpu_state.sprs[SPR_PMR] &= ~(SPR_PMR_DME | SPR_PMR_SME);
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TRACE("Asserting interrupt %d (%s).\n", line, getsprbit(SPR_PICMR, line) ? "Unmasked" : "Masked");
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TRACE("Asserting interrupt %d (%s).\n", line,
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(cpu_state.sprs[SPR_PICMR] & (1 << line)) ? "Unmasked" : "Masked");
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if (getsprbit(SPR_PICMR, line) || line < 2) {
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if ((cpu_state.sprs[SPR_PICMR] & (1 << line)) || line < 2) {
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setsprbit(SPR_PICSR, line, 1);
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cpu_state.sprs[SPR_PICSR] |= 1 << line;
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/* Don't do anything if interrupts not currently enabled */
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/* Don't do anything if interrupts not currently enabled */
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if (testsprbits (SPR_SR, SPR_SR_IEE)) {
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if (cpu_state.sprs[SPR_SR] & SPR_SR_IEE) {
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TRACE("Delivering interrupt on cycle %lli\n", runtime.sim.cycles);
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TRACE("Delivering interrupt on cycle %lli\n", runtime.sim.cycles);
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except_handle(EXCEPT_INT, mfspr(SPR_EEAR_BASE));
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except_handle(EXCEPT_INT, cpu_state.sprs[SPR_EEAR_BASE]);
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} else
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} else
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/* Interrupts not currently enabled, retry next clock cycle */
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/* Interrupts not currently enabled, retry next clock cycle */
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SCHED_ADD(pic_clock, (void *)line, 1);
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SCHED_ADD(pic_clock, (void *)line, 1);
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}
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}
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}
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}
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