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https://opencores.org/ocsvn/or1k/or1k/trunk
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| Rev 257 |
Rev 261 |
| Line 43... |
Line 43... |
int bpb_sim;
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int bpb_sim;
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int btic_sim;
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int btic_sim;
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} bp; /* Branch prediction */
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} bp; /* Branch prediction */
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int clkcycle_ns; /* Clock cycle in nanoseconds */
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int clkcycle_ns; /* Clock cycle in nanoseconds */
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int nuarts;
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int uarts_enabled;
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struct {
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struct {
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char *rxfile; /* File for RX */
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char rxfile[STR_SIZE]; /* File for RX */
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char *txfile; /* File for TX (required) */
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char txfile[STR_SIZE]; /* File for TX (required) */
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int jitter; /* CZ 250801 - in msecs...time to block */
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int jitter; /* CZ 250801 - in msecs...time to block */
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unsigned long baseaddr; /* Naturally aligned base address */
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unsigned long baseaddr; /* Naturally aligned base address */
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} uarts[NR_UARTS];
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} uarts[NR_UARTS];
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int ndmas;
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int dmas_enabled;
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struct {
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struct {
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unsigned long baseaddr;
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unsigned long baseaddr;
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unsigned irq;
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unsigned irq;
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} dmas[NR_DMAS];
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} dmas[NR_DMAS];
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Line 69... |
char *rxfile;
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char *rxfile;
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char *txfile;
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char *txfile;
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} ethernets[NR_ETHERNETS];
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} ethernets[NR_ETHERNETS];
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struct {
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struct {
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int enabled; /* is MC enabled? */
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unsigned long baseaddr; /* Naturally aligned base address */
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char memory_table_file[STR_SIZE]; /* Memory table filename */
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char memory_table_file[STR_SIZE]; /* Memory table filename */
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int enable; /* is MC enabled? */
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unsigned POC; /* power on reset configuration register */
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unsigned POC; /* power on reset configuration register */
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} mc;
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} mc;
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int simdebug; /* Simulator debugging */
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int simdebug; /* Simulator debugging */
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int profile; /* Is profiler running */
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int profile; /* Is profiler running */
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