| Line 103... |
Line 103... |
uorreg_t ttmr = cpu_state.sprs[SPR_TTMR];
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uorreg_t ttmr = cpu_state.sprs[SPR_TTMR];
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uint32_t match_time = ttmr & SPR_TTMR_PERIOD;
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uint32_t match_time = ttmr & SPR_TTMR_PERIOD;
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uint32_t ttcr_period = spr_read_ttcr() & SPR_TTCR_PERIOD;
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uint32_t ttcr_period = spr_read_ttcr() & SPR_TTCR_PERIOD;
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|
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/* Remove previous jobs if they exists */
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/* Remove previous jobs if they exists */
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if(prev_ttmr & SPR_TTMR_IE)
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if((prev_ttmr & SPR_TTMR_IE) && !(ttmr & SPR_TTMR_IP))
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SCHED_FIND_REMOVE(tick_raise_except, NULL);
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SCHED_FIND_REMOVE(tick_raise_except, NULL);
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|
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switch(prev_ttmr & SPR_TTMR_M) {
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switch(prev_ttmr & SPR_TTMR_M) {
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case SPR_TTMR_RT:
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case SPR_TTMR_RT:
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SCHED_FIND_REMOVE(tick_restart, NULL);
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SCHED_FIND_REMOVE(tick_restart, NULL);
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| Line 167... |
Line 167... |
{
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{
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uorreg_t value = cpu_state.sprs[SPR_TTMR];
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uorreg_t value = cpu_state.sprs[SPR_TTMR];
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|
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TRACE("set ttmr = %"PRIxREG" (previous: %"PRIxREG")\n", value, prev_val);
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TRACE("set ttmr = %"PRIxREG" (previous: %"PRIxREG")\n", value, prev_val);
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|
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if(value & SPR_TTMR_IP) {
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if(prev_val & SPR_TTMR_IP)
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/* SPR_TTMR_IP has not been cleared, continue sending timer interrupts */
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SCHED_ADD(tick_raise_except, NULL, 0);
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else
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/* Code running on or1k can't set SPR_TTMR_IP so make sure it isn't */
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/* Code running on or1k can't set SPR_TTMR_IP so make sure it isn't */
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cpu_state.sprs[SPR_TTMR] &= ~SPR_TTMR_IP;
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cpu_state.sprs[SPR_TTMR] &= ~SPR_TTMR_IP;
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}
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|
|
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/* If the timer was already disabled, ttcr should not be updated */
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/* If the timer was already disabled, ttcr should not be updated */
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if(tick_count)
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if(tick_count)
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cpu_state.sprs[SPR_TTCR] = runtime.sim.cycles - cycles_start;
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cpu_state.sprs[SPR_TTCR] = runtime.sim.cycles - cycles_start;
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|
|
