OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [stable_0_2_0_rc2/] [or1ksim/] [toplevel.c] - Diff between revs 463 and 479

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 463 Rev 479
Line 44... Line 44...
#include "execute.h"
#include "execute.h"
#include "sim-config.h"
#include "sim-config.h"
#include "spr_defs.h"
#include "spr_defs.h"
#include "dma.h"
#include "dma.h"
#include "vapi.h"
#include "vapi.h"
 
 
#include "coff.h"
 
 
 
#include "gdbcomm.h"
#include "gdbcomm.h"
 
#include "debug_unit.h"
 
#include "coff.h"
 
 
/* CVS revision number. */
/* CVS revision number. */
const char rcsrev[] = "$Revision: 1.53 $";
const char rcsrev[] = "$Revision: 1.54 $";
 
 
/* Continuos run versus single step tracing switch. */
/* Continuos run versus single step tracing switch. */
int cont_run;
int cont_run;
 
 
/* History of execution */
/* History of execution */
Line 95... Line 94...
}
}
 
 
void ctrl_c(signum)
void ctrl_c(signum)
     int signum;
     int signum;
{
{
  extern int cpu_stalled;  /* CZ from debug_interface */
 
  cont_run = cpu_stalled ? 0 : 1;
  cont_run = cpu_stalled ? 0 : 1;
  config.sim.iprompt = 1;
  config.sim.iprompt = 1;
  cpu_stalled = 0;
  set_stall_state (0);
  signal(SIGINT, ctrl_c);
  signal(SIGINT, ctrl_c);
}
}
 
 
void version()
void version()
{
{
Line 149... Line 147...
  printf("help       - available commands (this list)\n");
  printf("help       - available commands (this list)\n");
}
}
 
 
void debugmem( unsigned long from, unsigned long to );
void debugmem( unsigned long from, unsigned long to );
 
 
 
/* Resets all subunits */
 
void sim_reset ()
 
{
 
  uart_reset();
 
  dma_reset();
 
  eth_reset();
 
  gpio_reset();
 
  tick_reset();
 
  pm_reset();
 
  pic_reset();
 
  mc_reset();
 
  du_reset ();
 
  reset();
 
}
 
 
/* Initalizes all devices and sim */
/* Initalizes all devices and sim */
void sim_init ()
void sim_init ()
{
{
  init_memory_table ();
  init_memory_table ();
  init_labels();
  init_labels();
  init_breakpoints();
  init_breakpoints();
  initstats();
  initstats();
  build_automata();
  build_automata();
 
 
  if (GDB_ENABLED)
 
    gdbcomm_init ();
 
 
 
  if (config.sim.profile) {
  if (config.sim.profile) {
    runtime.sim.fprof = fopen(config.sim.prof_fn, "wt+");
    runtime.sim.fprof = fopen(config.sim.prof_fn, "wt+");
    if(!runtime.sim.fprof) {
    if(!runtime.sim.fprof) {
      config.sim.profile = 0;
      config.sim.profile = 0;
      fprintf(stderr, "WARNING: Problems opening profile file. Profiling disabled. \n");
      fprintf(stderr, "WARNING: Problems opening profile file. Profiling disabled. \n");
Line 223... Line 233...
    config.debug.gdb_enabled = 0;
    config.debug.gdb_enabled = 0;
    if (config.sim.verbose)
    if (config.sim.verbose)
      fprintf (stderr, "WARNING: Debug module not enabled, cannot start gdb.\n");
      fprintf (stderr, "WARNING: Debug module not enabled, cannot start gdb.\n");
  }
  }
 
 
 
  if (GDB_ENABLED)
 
    gdbcomm_init ();
 
 
  /* Enable dependency stats, if we want to do history analisis */
  /* Enable dependency stats, if we want to do history analisis */
  if (config.sim.history && !config.cpu.dependstats) {
  if (config.sim.history && !config.cpu.dependstats) {
    config.cpu.dependstats = 1;
    config.cpu.dependstats = 1;
    if (config.sim.verbose)
    if (config.sim.verbose)
      fprintf (stderr, "WARNING: dependstats stats must be enabled to do history analisis.\n");
      fprintf (stderr, "WARNING: dependstats stats must be enabled to do history analisis.\n");
Line 244... Line 257...
    if (config.sim.verbose)
    if (config.sim.verbose)
      printf ("VAPI started, waiting for clients.\n");
      printf ("VAPI started, waiting for clients.\n");
  }
  }
  lock_memory_table ();
  lock_memory_table ();
 
 
  uart_reset();
  sim_reset ();
  dma_reset();
 
  eth_reset();
 
  gpio_reset();
 
  tick_reset();
 
  pm_reset();
 
  pic_reset();
 
  mc_reset();
 
  reset();
 
 
 
  /* Wait till all test are connected.  */
  /* Wait till all test are connected.  */
  if (config.vapi.enabled) {
  if (config.vapi.enabled) {
    int numu = vapi_num_unconnected (0);
    int numu = vapi_num_unconnected (0);
    if (numu) {
    if (numu) {
Line 565... Line 570...
      else
      else
        hush = 0;
        hush = 0;
      cont_run = strtol(item2, NULL, 0);
      cont_run = strtol(item2, NULL, 0);
    } else
    } else
    if(!strcmp(item1, "stall")) { /* Added by CZ 210801 */
    if(!strcmp(item1, "stall")) { /* Added by CZ 210801 */
      extern int cpu_stalled;  /* CZ from debug_interface */
      set_stall_state (1);
      cpu_stalled = 1;
 
      config.sim.iprompt = 0;
      config.sim.iprompt = 0;
      cont_run = -1;
      cont_run = -1;
      hush = 1;
      hush = 1;
    } else
    } else
    if (!strcmp(item1, "trace")) { /* Added by CZ 210801 */
    if (!strcmp(item1, "trace")) { /* Added by CZ 210801 */
Line 623... Line 627...
 
 
    /* MM: 'run -1' means endless execution.  */
    /* MM: 'run -1' means endless execution.  */
    while(cont_run != 0) {
    while(cont_run != 0) {
      int debug_slowdown = DEBUG_SLOWDOWN;
      int debug_slowdown = DEBUG_SLOWDOWN;
      extern int cycle_delay;  /* Added by CZ 27/05/01. Set during exception. */
      extern int cycle_delay;  /* Added by CZ 27/05/01. Set during exception. */
      extern int cpu_stalled;  /* CZ from debug_interface */
 
 
 
      if (cpu_stalled)
      if (cpu_stalled) {
 
        printf ("!");
        if(GDB_ENABLED) {
        if(GDB_ENABLED) {
          BlockJTAG();
          BlockJTAG();
          HandleServerSocket(false);
          HandleServerSocket(false);
          continue;
 
        } else
        } else
          fprintf (stderr, "WARNING: CPU stalled and gdb connection not enabled.");
          fprintf (stderr, "WARNING: CPU stalled and gdb connection not enabled.");
 
        continue;
 
      }
 
 
      if (!testsprbits(SPR_PMR, SPR_PMR_DME | SPR_PMR_SME)) {
      if (!testsprbits(SPR_PMR, SPR_PMR_DME | SPR_PMR_SME)) {
        pic_clock();
        pic_clock();
        if(cycle_delay <= 0) {
        if(cycle_delay <= 0) {
          unsigned int addr;
          unsigned int addr;
Line 695... Line 700...
      if (config.dmas_enabled) dma_clock();
      if (config.dmas_enabled) dma_clock();
      if (config.ethernets_enabled) eth_clock();
      if (config.ethernets_enabled) eth_clock();
      if (config.gpios_enabled) gpio_clock();
      if (config.gpios_enabled) gpio_clock();
      if (config.sim.exe_log) dump_exe_log();
      if (config.sim.exe_log) dump_exe_log();
      if (config.vapi.enabled) vapi_check();
      if (config.vapi.enabled) vapi_check();
      if (GDB_ENABLED && debug_slowdown-- == 0) {
      if (GDB_ENABLED) {// && ((debug_slowdown--) <= 0)) {
        debug_slowdown = DEBUG_SLOWDOWN;
        debug_slowdown = DEBUG_SLOWDOWN;
        HandleServerSocket(false); /* block & check_stdin = false */
        HandleServerSocket(false); /* block & check_stdin = false */
 
        debug (1, ".");
      }
      }
 
      if (DEBUG_ENABLED)
 
        if (testsprbits(SPR_DMR1, SPR_DMR1_ST)) set_stall_state (1);
    }
    }
    hush = 0;
    hush = 0;
    fflush(stdout);
    fflush(stdout);
    freopen("/dev/fd/0", "w+", stdout);
    freopen("/dev/fd/0", "w+", stdout);
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.