| Line 69... |
Line 69... |
#if DYNAMIC_EXECUTION
|
#if DYNAMIC_EXECUTION
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PRINTF("FIXME: Emulating a stalled cpu not implemented (in the dynamic execution model)\n");
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PRINTF("FIXME: Emulating a stalled cpu not implemented (in the dynamic execution model)\n");
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#endif
|
#endif
|
development.riscop &= ~RISCOP_STALL;
|
development.riscop &= ~RISCOP_STALL;
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development.riscop |= state ? RISCOP_STALL : 0;
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development.riscop |= state ? RISCOP_STALL : 0;
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if(testsprbits(SPR_DMR1, SPR_DMR1_DXFW)) /* If debugger disabled */
|
if(cpu_state.sprs[SPR_DMR1] & SPR_DMR1_DXFW) /* If debugger disabled */
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state = 0;
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state = 0;
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runtime.cpu.stalled = state;
|
runtime.cpu.stalled = state;
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}
|
}
|
|
|
void du_reset()
|
void du_reset()
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| Line 92... |
Line 92... |
/* Do not stop, if we have debug module disabled or during reset */
|
/* Do not stop, if we have debug module disabled or during reset */
|
if(!config.debug.enabled || in_reset)
|
if(!config.debug.enabled || in_reset)
|
return 0;
|
return 0;
|
|
|
/* If we're single stepping, always stop */
|
/* If we're single stepping, always stop */
|
if((action == DebugInstructionFetch) && testsprbits (SPR_DMR1, SPR_DMR1_ST))
|
if((action == DebugInstructionFetch) && (cpu_state.sprs[SPR_DMR1] & SPR_DMR1_ST))
|
return 1;
|
return 1;
|
|
|
/* is any watchpoint enabled to generate a break or count? If not, ignore */
|
/* is any watchpoint enabled to generate a break or count? If not, ignore */
|
if(mfspr(SPR_DMR2) & (SPR_DMR2_WGB | SPR_DMR2_AWTC))
|
if(mfspr(SPR_DMR2) & (SPR_DMR2_WGB | SPR_DMR2_AWTC))
|
return calculate_watchpoints(action, udata);
|
return calculate_watchpoints(action, udata);
|
| Line 163... |
Line 163... |
switch(i) {
|
switch(i) {
|
case 0:
|
case 0:
|
chain1 = chain2 = DCR_hit;
|
chain1 = chain2 = DCR_hit;
|
break;
|
break;
|
case 8:
|
case 8:
|
chain1 = getsprbits(SPR_DWCR0, SPR_DWCR_COUNT) == getsprbits(SPR_DWCR0,
|
chain1 = (cpu_state.sprs[SPR_DWCR0] & SPR_DWCR_COUNT) ==
|
SPR_DWCR_MATCH);
|
(cpu_state.sprs[SPR_DWCR0] & SPR_DWCR_MATCH);
|
chain2 = watchpoints & (1 << 7);
|
chain2 = watchpoints & (1 << 7);
|
break;
|
break;
|
case 9:
|
case 9:
|
chain1 = getsprbits(SPR_DWCR1, SPR_DWCR_COUNT) == getsprbits (SPR_DWCR1,
|
chain1 = (cpu_state.sprs[SPR_DWCR1] & SPR_DWCR_COUNT) ==
|
SPR_DWCR_MATCH);
|
(cpu_state.sprs[SPR_DWCR1] & SPR_DWCR_MATCH);
|
chain2 = watchpoints & (1 << 8);
|
chain2 = watchpoints & (1 << 8);
|
break;
|
break;
|
case 10:
|
case 10:
|
/* TODO: External watchpoint - not yet handled! */
|
/* TODO: External watchpoint - not yet handled! */
|
#if 0
|
#if 0
|
| Line 187... |
Line 187... |
chain1 = DCR_hit;
|
chain1 = DCR_hit;
|
chain2 = watchpoints & (bit >> 1);
|
chain2 = watchpoints & (bit >> 1);
|
break;
|
break;
|
}
|
}
|
|
|
switch(getsprbits(SPR_DMR1, SPR_DMR1_CW0 << i)) {
|
switch((cpu_state.sprs[SPR_DMR1] >> i) & SPR_DMR1_CW0) {
|
case 0: match = chain1; break;
|
case 0: match = chain1; break;
|
case 1: match = chain1 && chain2; break;
|
case 1: match = chain1 && chain2; break;
|
case 2: match = chain1 || chain2; break;
|
case 2: match = chain1 || chain2; break;
|
}
|
}
|
|
|
/* Increment counters & generate counter break */
|
/* Increment counters & generate counter break */
|
if(match) {
|
if(match) {
|
/* watchpoint did not appear before in this clock cycle */
|
/* watchpoint did not appear before in this clock cycle */
|
if(!(watchpoints & bit)) {
|
if(!(watchpoints & bit)) {
|
int counter = (getsprbits(SPR_DMR2, SPR_DMR2_AWTC) & bit) ? 1 : 0;
|
int counter = (((cpu_state.sprs[SPR_DMR2] & SPR_DMR2_AWTC) >> 2) & bit) ? 1 : 0;
|
int enabled = counter ? getsprbits(SPR_DMR2, SPR_DMR2_WCE1) :
|
int enabled = cpu_state.sprs[SPR_DMR2] & (counter ? SPR_DMR2_WCE1 : SPR_DMR2_WCE0);
|
getsprbits(SPR_DMR2, SPR_DMR2_WCE0);
|
if(enabled) {
|
if(enabled)
|
uorreg_t count = cpu_state.sprs[SPR_DWCR0 + counter];
|
setsprbits(SPR_DWCR0 + counter, SPR_DWCR_COUNT,
|
count = (count & ~SPR_DWCR_COUNT) | ((count & SPR_DWCR_COUNT) + 1);
|
getsprbits(SPR_DWCR0 + counter, SPR_DWCR_COUNT) + 1);
|
cpu_state.sprs[SPR_DWCR0 + counter] = count;
|
|
}
|
watchpoints |= bit;
|
watchpoints |= bit;
|
}
|
}
|
|
|
/* should this watchpoint generate a breakpoint? */
|
/* should this watchpoint generate a breakpoint? */
|
if(getsprbits(SPR_DMR2, SPR_DMR2_WGB) & bit)
|
if(((cpu_state.sprs[SPR_DMR2] & SPR_DMR2_WGB) >> 13) & bit)
|
breakpoint = 1;
|
breakpoint = 1;
|
}
|
}
|
}
|
}
|
|
|
return breakpoint;
|
return breakpoint;
|
