| Line 87... |
Line 87... |
#define UART_DLL 0 /* R/W: Divisor Latch Low, DLAB=1 */
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#define UART_DLL 0 /* R/W: Divisor Latch Low, DLAB=1 */
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#define UART_DLH 1 /* R/W: Divisor Latch High, DLAB=1 */
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#define UART_DLH 1 /* R/W: Divisor Latch High, DLAB=1 */
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#define UART_IER 1 /* R/W: Interrupt Enable Register */
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#define UART_IER 1 /* R/W: Interrupt Enable Register */
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#define UART_IIR 2 /* R: Interrupt ID Register */
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#define UART_IIR 2 /* R: Interrupt ID Register */
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#define UART_LCR 3 /* R/W: Line Control Register */
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#define UART_LCR 3 /* R/W: Line Control Register */
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#define UART_MCR 4 /* R/W: Modem Control Register */
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#define UART_MCR 4 /* W: Modem Control Register */
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#define UART_LSR 5 /* R: Line Status Register */
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#define UART_LSR 5 /* R: Line Status Register */
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#define UART_MSR 6 /* R: Modem Status Register */
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#define UART_MSR 6 /* R: Modem Status Register */
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#define UART_SCR 7 /* R/W: Scratch Register */
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#define UART_SCR 7 /* R/W: Scratch Register */
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/*
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/*
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Line 117... |
#define UART_LCR_STOP 0x04 /* Stop bits: 0=1 stop bit, 1= 2 stop bits */
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#define UART_LCR_STOP 0x04 /* Stop bits: 0=1 stop bit, 1= 2 stop bits */
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#define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */
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#define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */
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#define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */
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#define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */
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#define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */
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#define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */
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#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
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#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
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#define UART_LCR_RESET 0x03
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/*
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/*
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* Bit definitions for the Line Status Register
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* Bit definitions for the Line Status Register
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*/
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*/
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#define UART_LSR_TXSERE 0x40 /* Transmitter serial register empty */
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#define UART_LSR_TXSERE 0x40 /* Transmitter serial register empty */
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#define UART_LSR_TXBUFE 0x20 /* Transmitter buffer register empty */
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#define UART_LSR_TXBUFE 0x20 /* Transmitter buffer register empty */
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