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Line 21... |
void uart_reset();
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void uart_reset();
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void uart_clock();
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void uart_clock();
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/* Definitions */
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/* Definitions */
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#define UART_ADDR_SPACE (8) /* UART memory address space size in bytes */
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#define UART_ADDR_SPACE (8) /* UART memory address space size in bytes */
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#define UART_RX_BUF (8192) /* VAPI should not send more that this amout of char before requesting something back */
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#define UART_MAX_FIFO_LEN (16) /* rx FIFO for uart 16550 */
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#define UART_MAX_FIFO_LEN (16) /* rx FIFO for uart 16550 */
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#define MAX_SKEW (1) /* max. clock skew in subclocks */
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#define MAX_SKEW (1) /* max. clock skew in subclocks */
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#define UART_VAPI_BUF_LEN 128 /* Size of VAPI command buffer - VAPI should not send more
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that this amout of char before requesting something back */
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#define UART_CLOCK_DIVIDER 16 /* Uart clock divider */
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/* Registers */
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/* Registers */
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struct dev_16450 {
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struct dev_16450 {
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struct {
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struct {
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unsigned char rxbuf[UART_MAX_FIFO_LEN];
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unsigned char rxbuf[UART_MAX_FIFO_LEN];
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unsigned char dll;
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unsigned char dll;
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unsigned char dlh;
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unsigned char dlh;
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unsigned char ier;
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unsigned char ier;
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unsigned char iir;
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unsigned char iir;
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unsigned char fcr;
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unsigned char lcr;
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unsigned char lcr;
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unsigned char mcr;
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unsigned char mcr;
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unsigned char lsr;
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unsigned char lsr;
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unsigned char msr;
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unsigned char msr;
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unsigned char scr;
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unsigned char scr;
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Line 58... |
int rxbuf_tail;
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int rxbuf_tail;
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unsigned int txser_full;
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unsigned int txser_full;
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unsigned int rxser_full;
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unsigned int rxser_full;
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unsigned int txbuf_full;
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unsigned int txbuf_full;
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unsigned int rxbuf_full;
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unsigned int rxbuf_full;
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unsigned char thre_int;
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unsigned thre_int;
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unsigned break_set;
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unsigned long txser_clks;
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unsigned long txser_clks;
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unsigned long rxser_clks;
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unsigned long rxser_clks;
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unsigned timeout_count;
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} istat; /* Internal status */
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} istat; /* Internal status */
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/* Clocks per char */
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/* Clocks per char */
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unsigned long char_clks;
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unsigned long char_clks;
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int skew;
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int skew;
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int next_break;
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int next_break;
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int next_break_cnt;
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int next_break_cnt;
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int cur_break;
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int cur_break;
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int cur_break_cnt;
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int cur_break_cnt;
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int break_sent;
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} vapi;
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} vapi;
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/* Required by VAPI - circular buffer */
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/* Required by VAPI - circular buffer */
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unsigned long vapi_buf[UART_RX_BUF]; /* Buffer to store incoming characters to,
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unsigned long vapi_buf[UART_VAPI_BUF_LEN]; /* Buffer to store incoming characters to,
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since we cannot handle them so fast - we
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since we cannot handle them so fast - we
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are serial */
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are serial */
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int vapi_buf_head_ptr; /* Where we write to */
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int vapi_buf_head_ptr; /* Where we write to */
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int vapi_buf_tail_ptr; /* Where we read from */
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int vapi_buf_tail_ptr; /* Where we read from */
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#define UART_TXBUF 0 /* W: Tx buffer, DLAB=0 */
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#define UART_TXBUF 0 /* W: Tx buffer, DLAB=0 */
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#define UART_DLL 0 /* R/W: Divisor Latch Low, DLAB=1 */
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#define UART_DLL 0 /* R/W: Divisor Latch Low, DLAB=1 */
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#define UART_DLH 1 /* R/W: Divisor Latch High, DLAB=1 */
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#define UART_DLH 1 /* R/W: Divisor Latch High, DLAB=1 */
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#define UART_IER 1 /* R/W: Interrupt Enable Register */
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#define UART_IER 1 /* R/W: Interrupt Enable Register */
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#define UART_IIR 2 /* R: Interrupt ID Register */
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#define UART_IIR 2 /* R: Interrupt ID Register */
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#define UART_FCR 2 /* W: FIFO Control Register */
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#define UART_LCR 3 /* R/W: Line Control Register */
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#define UART_LCR 3 /* R/W: Line Control Register */
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#define UART_MCR 4 /* W: Modem Control Register */
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#define UART_MCR 4 /* W: Modem Control Register */
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#define UART_LSR 5 /* R: Line Status Register */
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#define UART_LSR 5 /* R: Line Status Register */
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#define UART_MSR 6 /* R: Modem Status Register */
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#define UART_MSR 6 /* R: Modem Status Register */
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#define UART_SCR 7 /* R/W: Scratch Register */
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#define UART_SCR 7 /* R/W: Scratch Register */
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/*
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/*
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* R/W masks for valid bits in 8250/16450 (mask out 16550 and later bits)
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* R/W masks for valid bits in 8250/16450 (mask out 16550 and later bits)
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*
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*
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*/
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*/
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#define UART_VALID_LCR 0xff
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#define UART_VALID_LCR 0xff
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#define UART_VALID_LSR 0x7f
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#define UART_VALID_LSR 0xff
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#define UART_VALID_IIR 0x07
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#define UART_VALID_IIR 0x0f
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#define UART_VALID_FCR 0xc0
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#define UART_VALID_IER 0x0f
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#define UART_VALID_IER 0x0f
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#define UART_VALID_MCR 0x1f
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#define UART_VALID_MCR 0x1f
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#define UART_VALID_MSR 0xff
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#define UART_VALID_MSR 0xff
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/*
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/*
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#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
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#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
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#define UART_LCR_RESET 0x03
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#define UART_LCR_RESET 0x03
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/*
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/*
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* Bit definitions for the Line Status Register
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* Bit definitions for the Line Status Register
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*/
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*/
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#define UART_LSR_RXERR 0x80 /* Error in rx fifo */
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#define UART_LSR_TXSERE 0x40 /* Transmitter serial register empty */
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#define UART_LSR_TXSERE 0x40 /* Transmitter serial register empty */
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#define UART_LSR_TXBUFE 0x20 /* Transmitter buffer register empty */
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#define UART_LSR_TXBUFE 0x20 /* Transmitter buffer register empty */
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#define UART_LSR_BREAK 0x10 /* Break interrupt indicator */
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#define UART_LSR_BREAK 0x10 /* Break interrupt indicator */
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#define UART_LSR_FRAME 0x08 /* Frame error indicator */
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#define UART_LSR_FRAME 0x08 /* Frame error indicator */
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#define UART_LSR_PARITY 0x04 /* Parity error indicator */
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#define UART_LSR_PARITY 0x04 /* Parity error indicator */
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#define UART_IIR_MSI 0x00 /* Modem status interrupt (Low priority) */
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#define UART_IIR_MSI 0x00 /* Modem status interrupt (Low priority) */
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#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
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#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
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#define UART_IIR_RDI 0x04 /* Receiver data interrupt */
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#define UART_IIR_RDI 0x04 /* Receiver data interrupt */
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#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt (High p.) */
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#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt (High p.) */
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#define UART_IIR_CTI 0x0c /* Character timeout */
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/*
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* Bit Definitions for the FIFO Control Register
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*/
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#define UART_FCR_FIE 0x01 /* FIFO enable */
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#define UART_FCR_RRXFI 0x02 /* Reset rx FIFO */
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#define UART_FCR_RTXFI 0x02 /* Reset tx FIFO */
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#define UART_FIFO_TRIGGER(x) /* Trigger values for indexes 0..3 */\
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((x)==0?1\
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:(x)==1?4\
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:(x)==2?8\
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:(x)==3?14:0)
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/*
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/*
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* Bit definitions for the Interrupt Enable Register
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* Bit definitions for the Interrupt Enable Register
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*/
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*/
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#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
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#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
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Line 208... |
#define UART_MSR_DCTS 0x01 /* Delta CTS */
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#define UART_MSR_DCTS 0x01 /* Delta CTS */
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/*
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/*
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* Various definitions
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* Various definitions
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*/
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*/
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#define MAX_BREAK_COUNT 12
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#define UART_BREAK_COUNT (4) /* # of chars to count when performing break */
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#define UART_CHAR_TIMEOUT (4) /* # of chars to count when performing timeout int. */
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No newline at end of file
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No newline at end of file
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