OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [stable_0_2_0_rc3/] [or1ksim/] [peripheral/] [dma.c] - Diff between revs 1467 and 1486

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 1467 Rev 1486
Line 120... Line 120...
/* Read a register */
/* Read a register */
uint32_t dma_read32( oraddr_t addr, void *dat )
uint32_t dma_read32( oraddr_t addr, void *dat )
{
{
  struct dma_controller *dma = dat;
  struct dma_controller *dma = dat;
 
 
  addr -= dma->baseaddr;
 
 
 
  if ( addr < DMA_CH_BASE ) {
  if ( addr < DMA_CH_BASE ) {
    /* case of global (not per-channel) registers */
    /* case of global (not per-channel) registers */
    switch( addr ) {
    switch( addr ) {
    case DMA_CSR: return dma->regs.csr;
    case DMA_CSR: return dma->regs.csr;
    case DMA_INT_MSK_A: return dma->regs.int_msk_a;
    case DMA_INT_MSK_A: return dma->regs.int_msk_a;
Line 175... Line 173...
/* Write a register */
/* Write a register */
void dma_write32( oraddr_t addr, uint32_t value, void *dat )
void dma_write32( oraddr_t addr, uint32_t value, void *dat )
{
{
  struct dma_controller *dma = dat;
  struct dma_controller *dma = dat;
 
 
  addr -= dma->baseaddr;
 
 
 
  /* case of global (not per-channel) registers */
  /* case of global (not per-channel) registers */
  if ( addr < DMA_CH_BASE ) {
  if ( addr < DMA_CH_BASE ) {
    switch( addr ) {
    switch( addr ) {
    case DMA_CSR:
    case DMA_CSR:
      if ( TEST_FLAG( value, DMA_CSR, PAUSE ) )
      if ( TEST_FLAG( value, DMA_CSR, PAUSE ) )
Line 506... Line 502...
 
 
void dma_sec_end(void *dat)
void dma_sec_end(void *dat)
{
{
  struct dma_controller *dma = dat;
  struct dma_controller *dma = dat;
  struct dma_controller *cur;
  struct dma_controller *cur;
 
  struct mem_ops ops;
 
 
  if(!dma->enabled) {
  if(!dma->enabled) {
    free(dat);
    free(dat);
    return;
    return;
  }
  }
 
 
  register_memoryarea( dma->baseaddr, DMA_ADDR_SPACE, 4, 0, dma_read32, dma_write32, dat );
  memset(&ops, 0, sizeof(struct mem_ops));
 
 
 
  ops.readfunc32 = dma_read32;
 
  ops.writefunc32 = dma_write32;
 
  ops.read_dat32 = dat;
 
  ops.write_dat32 = dat;
 
 
 
  /* FIXME: Correct delay?? */
 
  ops.delayr = 2;
 
  ops.delayw = 2;
 
 
 
  reg_mem_area( dma->baseaddr, DMA_ADDR_SPACE, 0, &ops );
  reg_sim_reset( dma_reset, dat );
  reg_sim_reset( dma_reset, dat );
  reg_sim_stat( dma_status, dat );
  reg_sim_stat( dma_status, dat );
 
 
  if(dmas) {
  if(dmas) {
    for(cur = dmas; cur->next; cur = cur->next);
    for(cur = dmas; cur->next; cur = cur->next);

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.