| Line 76... |
Line 76... |
* Responsible for starting and finishing TX
|
* Responsible for starting and finishing TX
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*/
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*/
|
void eth_controller_tx_clock( void *dat )
|
void eth_controller_tx_clock( void *dat )
|
{
|
{
|
struct eth_device *eth = dat;
|
struct eth_device *eth = dat;
|
int breakpoint = 0;
|
|
int bAdvance = 1;
|
int bAdvance = 1;
|
#if HAVE_ETH_PHY
|
#if HAVE_ETH_PHY
|
struct sockaddr_ll sll;
|
struct sockaddr_ll sll;
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#endif /* HAVE_ETH_PHY */
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#endif /* HAVE_ETH_PHY */
|
long nwritten = 0;
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long nwritten = 0;
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| Line 155... |
Line 154... |
/* stay in this state if (TXEN && !READY) */
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/* stay in this state if (TXEN && !READY) */
|
break;
|
break;
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case ETH_TXSTATE_READFIFO:
|
case ETH_TXSTATE_READFIFO:
|
#if 1
|
#if 1
|
if ( eth->tx.bytes_sent < eth->tx.packet_length ) {
|
if ( eth->tx.bytes_sent < eth->tx.packet_length ) {
|
read_word = eval_direct32(eth->tx.bytes_sent + eth->tx.bd_addr, &breakpoint, 0, 0);
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read_word = eval_direct32(eth->tx.bytes_sent + eth->tx.bd_addr, 0, 0);
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eth->tx_buff[eth->tx.bytes_sent] = (unsigned char)(read_word >> 24);
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eth->tx_buff[eth->tx.bytes_sent] = (unsigned char)(read_word >> 24);
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eth->tx_buff[eth->tx.bytes_sent+1] = (unsigned char)(read_word >> 16);
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eth->tx_buff[eth->tx.bytes_sent+1] = (unsigned char)(read_word >> 16);
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eth->tx_buff[eth->tx.bytes_sent+2] = (unsigned char)(read_word >> 8);
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eth->tx_buff[eth->tx.bytes_sent+2] = (unsigned char)(read_word >> 8);
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eth->tx_buff[eth->tx.bytes_sent+3] = (unsigned char)(read_word);
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eth->tx_buff[eth->tx.bytes_sent+3] = (unsigned char)(read_word);
|
eth->tx.bytes_sent += 4;
|
eth->tx.bytes_sent += 4;
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}
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}
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#else
|
#else
|
if ( eth->tx.bytes_sent < eth->tx.packet_length ) {
|
if ( eth->tx.bytes_sent < eth->tx.packet_length ) {
|
eth->tx_buff[eth->tx.bytes_sent] = eval_direct8(eth->tx.bytes_sent + eth->tx.bd_addr, &breakpoint, 0, 0);
|
eth->tx_buff[eth->tx.bytes_sent] = eval_direct8(eth->tx.bytes_sent + eth->tx.bd_addr, 0, 0);
|
eth->tx.bytes_sent += 1;
|
eth->tx.bytes_sent += 1;
|
}
|
}
|
#endif
|
#endif
|
else {
|
else {
|
TRACE ("TX - entering state TRANSMIT\n");
|
TRACE ("TX - entering state TRANSMIT\n");
|
| Line 248... |
Line 247... |
* Responsible for starting and finishing RX
|
* Responsible for starting and finishing RX
|
*/
|
*/
|
void eth_controller_rx_clock( void *dat )
|
void eth_controller_rx_clock( void *dat )
|
{
|
{
|
struct eth_device *eth = dat;
|
struct eth_device *eth = dat;
|
int breakpoint = 0;
|
|
long nread;
|
long nread;
|
unsigned long send_word;
|
unsigned long send_word;
|
|
|
|
|
switch (eth->rx.state) {
|
switch (eth->rx.state) {
|
| Line 391... |
Line 389... |
#if 1
|
#if 1
|
send_word = ((unsigned long)eth->rx_buff[eth->rx.bytes_read] << 24) |
|
send_word = ((unsigned long)eth->rx_buff[eth->rx.bytes_read] << 24) |
|
((unsigned long)eth->rx_buff[eth->rx.bytes_read+1] << 16) |
|
((unsigned long)eth->rx_buff[eth->rx.bytes_read+1] << 16) |
|
((unsigned long)eth->rx_buff[eth->rx.bytes_read+2] << 8) |
|
((unsigned long)eth->rx_buff[eth->rx.bytes_read+2] << 8) |
|
((unsigned long)eth->rx_buff[eth->rx.bytes_read+3] );
|
((unsigned long)eth->rx_buff[eth->rx.bytes_read+3] );
|
set_direct32( eth->rx.bd_addr + eth->rx.bytes_read, send_word, &breakpoint, 0, 0);
|
set_direct32( eth->rx.bd_addr + eth->rx.bytes_read, send_word, 0, 0);
|
/* update counters */
|
/* update counters */
|
TRACE ("Write %ld, left %ld - %08lXd\n", eth->rx.bytes_read,
|
TRACE ("Write %ld, left %ld - %08lXd\n", eth->rx.bytes_read,
|
eth->rx.bytes_left, send_word);
|
eth->rx.bytes_left, send_word);
|
eth->rx.bytes_left -= 4;
|
eth->rx.bytes_left -= 4;
|
eth->rx.bytes_read += 4;
|
eth->rx.bytes_read += 4;
|
#else
|
#else
|
set_direct8( eth->rx.bd_addr + eth->rx.bytes_read, eth->rx_buff[eth->rx.bytes_read], &breakpoint, 0, 0);
|
set_direct8( eth->rx.bd_addr + eth->rx.bytes_read, eth->rx_buff[eth->rx.bytes_read], 0, 0);
|
eth->rx.bytes_left -= 1;
|
eth->rx.bytes_left -= 1;
|
eth->rx.bytes_read += 1;
|
eth->rx.bytes_read += 1;
|
#endif
|
#endif
|
|
|
if ( eth->rx.bytes_left <= 0 ) {
|
if ( eth->rx.bytes_left <= 0 ) {
|
