| Line 80... |
Line 80... |
/* Wishbone read */
|
/* Wishbone read */
|
uint32_t gpio_read32( oraddr_t addr, void *dat )
|
uint32_t gpio_read32( oraddr_t addr, void *dat )
|
{
|
{
|
struct gpio_device *gpio = dat;
|
struct gpio_device *gpio = dat;
|
|
|
addr -= gpio->baseaddr;
|
|
|
|
switch( addr ) {
|
switch( addr ) {
|
case RGPIO_IN: return gpio->curr.in | gpio->curr.out;
|
case RGPIO_IN: return gpio->curr.in | gpio->curr.out;
|
case RGPIO_OUT: return gpio->curr.out;
|
case RGPIO_OUT: return gpio->curr.out;
|
case RGPIO_OE: return gpio->curr.oe;
|
case RGPIO_OE: return gpio->curr.oe;
|
case RGPIO_INTE: return gpio->curr.inte;
|
case RGPIO_INTE: return gpio->curr.inte;
|
| Line 102... |
Line 100... |
/* Wishbone write */
|
/* Wishbone write */
|
void gpio_write32( oraddr_t addr, uint32_t value, void *dat )
|
void gpio_write32( oraddr_t addr, uint32_t value, void *dat )
|
{
|
{
|
struct gpio_device *gpio = dat;
|
struct gpio_device *gpio = dat;
|
|
|
addr -= gpio->baseaddr;
|
|
|
|
switch( addr ) {
|
switch( addr ) {
|
case RGPIO_IN: debug( 5, "GPIO: Cannot write to RGPIO_IN\n" ); break;
|
case RGPIO_IN: debug( 5, "GPIO: Cannot write to RGPIO_IN\n" ); break;
|
case RGPIO_OUT: gpio->next.out = value; break;
|
case RGPIO_OUT: gpio->next.out = value; break;
|
case RGPIO_OE: gpio->next.oe = value; break;
|
case RGPIO_OE: gpio->next.oe = value; break;
|
case RGPIO_INTE: gpio->next.inte = value; break;
|
case RGPIO_INTE: gpio->next.inte = value; break;
|
| Line 275... |
Line 271... |
}
|
}
|
|
|
void gpio_sec_end(void *dat)
|
void gpio_sec_end(void *dat)
|
{
|
{
|
struct gpio_device *gpio = dat;
|
struct gpio_device *gpio = dat;
|
|
struct mem_ops ops;
|
|
|
if(!gpio->enabled) {
|
if(!gpio->enabled) {
|
free(dat);
|
free(dat);
|
return;
|
return;
|
}
|
}
|
|
|
|
memset(&ops, 0, sizeof(struct mem_ops));
|
|
|
|
ops.readfunc32 = gpio_read32;
|
|
ops.writefunc32 = gpio_write32;
|
|
ops.write_dat32 = dat;
|
|
ops.read_dat32 = dat;
|
|
|
|
/* FIXME: Correct delays? */
|
|
ops.delayr = 2;
|
|
ops.delayw = 2;
|
|
|
/* Register memory range */
|
/* Register memory range */
|
register_memoryarea( gpio->baseaddr, GPIO_ADDR_SPACE, 4, 0, gpio_read32, gpio_write32, dat );
|
reg_mem_area( gpio->baseaddr, GPIO_ADDR_SPACE, 0, &ops );
|
|
|
reg_sim_reset(gpio_reset, dat);
|
reg_sim_reset(gpio_reset, dat);
|
reg_sim_stat(gpio_status, dat);
|
reg_sim_stat(gpio_status, dat);
|
}
|
}
|
|
|
