| Line 41... |
Line 41... |
#include "mc.h"
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#include "mc.h"
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#include "abstract.h"
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#include "abstract.h"
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#include "sim-config.h"
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#include "sim-config.h"
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#include "debug.h"
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#include "debug.h"
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extern struct dev_memarea *dev_list;
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struct mc_area {
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struct dev_memarea *mem;
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unsigned int cs;
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int mc;
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struct mc_area *next;
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};
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struct mc {
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unsigned long csr;
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unsigned long poc;
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unsigned long ba_mask;
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unsigned long csc[N_CE];
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unsigned long tms[N_CE];
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oraddr_t baseaddr;
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int enabled;
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/* Index of this memory controler amongst all the memory controlers */
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int index;
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/* List of memory devices under this mc's control */
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struct mc_area *mc_areas;
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struct mc *next;
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};
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static struct mc *mcs = NULL;
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/* List used to temporarily hold memory areas registered with the mc, while the
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* mc configureation has not been loaded */
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static struct mc_area *mc_areas = NULL;
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void set_csc_tms (int cs, unsigned long csc, unsigned long tms, struct mc *mc) {
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void set_csc_tms (int cs, unsigned long csc, unsigned long tms, struct mc *mc)
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struct dev_memarea *mem_dev = dev_list;
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{
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struct mc_area *cur = mc->mc_areas;
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while (mem_dev) {
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while (cur) {
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if (mem_dev->chip_select == cs) {
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if (cur->cs == cs) {
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mem_dev->addr_mask = mc->ba_mask << 22;
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/* FIXME: No peripheral should _ever_ acess a dev_memarea structure
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mem_dev->addr_compare = ((csc >> MC_CSC_SEL_OFFSET) /* & 0xff*/) << 22;
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* directly */
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mem_dev->valid = (csc >> MC_CSC_EN_OFFSET) & 0x01;
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cur->mem->addr_mask = mc->ba_mask << 22;
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cur->mem->addr_compare = ((csc >> MC_CSC_SEL_OFFSET) /* & 0xff*/) << 22;
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set_mem_valid(cur->mem, (csc >> MC_CSC_EN_OFFSET) & 0x01);
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if ((csc >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_ASYNC) {
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if ((csc >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_ASYNC) {
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mem_dev->delayr = (tms & 0xff) + ((tms >> 8) & 0x0f);
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adjust_rw_delay(cur->mem, (tms & 0xff) + ((tms >> 8) & 0x0f),
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mem_dev->delayw = ((tms >> 12) & 0x0f) + ((tms >> 16) & 0x0f) + ((tms >> 20) & 0x3f);
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((tms >> 12) & 0x0f) + ((tms >> 16) & 0x0f) + ((tms >> 20) & 0x3f));
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} else if ((csc >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_SDRAM) {
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} else if ((csc >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_SDRAM) {
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mem_dev->delayr = 3 + ((tms >> 4) & 0x03);
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adjust_rw_delay(cur->mem, 3 + ((tms >> 4) & 0x03),
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mem_dev->delayw = 3 + ((tms >> 4) & 0x03);
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3 + ((tms >> 4) & 0x03));
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} else if ((csc >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_SSRAM) {
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} else if ((csc >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_SSRAM) {
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mem_dev->delayr = 2;
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adjust_rw_delay(cur->mem, 2, 2);
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mem_dev->delayw = 2;
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} else if ((csc >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_SYNC) {
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} else if ((csc >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_SYNC) {
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mem_dev->delayr = 2;
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adjust_rw_delay(cur->mem, 2, 2);
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mem_dev->delayw = 2;
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}
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}
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return;
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return;
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}
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}
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mem_dev = mem_dev->next;
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cur = cur->next;
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}
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}
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}
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}
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/* Set a specific MC register with value. */
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/* Set a specific MC register with value. */
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void mc_write_word(oraddr_t addr, uint32_t value, void *dat)
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void mc_write_word(oraddr_t addr, uint32_t value, void *dat)
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| Line 79... |
Line 108... |
struct mc *mc = dat;
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struct mc *mc = dat;
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int chipsel;
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int chipsel;
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debug(5, "mc_write_word(%"PRIxADDR",%08"PRIx32")\n", addr, value);
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debug(5, "mc_write_word(%"PRIxADDR",%08"PRIx32")\n", addr, value);
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addr -= mc->baseaddr;
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switch (addr) {
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switch (addr) {
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case MC_CSR:
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case MC_CSR:
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mc->csr = value;
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mc->csr = value;
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break;
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break;
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case MC_POC:
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case MC_POC:
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| Line 116... |
Line 143... |
struct mc *mc = dat;
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struct mc *mc = dat;
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uint32_t value = 0;
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uint32_t value = 0;
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debug(5, "mc_read_word(%"PRIxADDR")", addr);
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debug(5, "mc_read_word(%"PRIxADDR")", addr);
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addr -= mc->baseaddr;
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switch (addr) {
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switch (addr) {
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case MC_CSR:
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case MC_CSR:
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value = mc->csr;
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value = mc->csr;
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break;
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break;
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case MC_POC:
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case MC_POC:
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| Line 147... |
Line 172... |
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/* Read POC register and init memory controler regs. */
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/* Read POC register and init memory controler regs. */
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void mc_reset(void *dat)
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void mc_reset(void *dat)
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{
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{
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struct mc *mc = dat;
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struct mc *mc = dat;
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struct dev_memarea *mem_dev = dev_list;
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struct mc_area *cur, *prev, *tmp;
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PRINTF("Resetting memory controller.\n");
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PRINTF("Resetting memory controller.\n");
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memset(mc->csc, 0, sizeof(mc->csc));
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memset(mc->csc, 0, sizeof(mc->csc));
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memset(mc->tms, 0, sizeof(mc->tms));
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memset(mc->tms, 0, sizeof(mc->tms));
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| Line 170... |
Line 195... |
mc->tms[0] = MC_TMS_SSRAM_VALID;
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mc->tms[0] = MC_TMS_SSRAM_VALID;
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} else if ((mc->csc[0] >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_SYNC) {
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} else if ((mc->csc[0] >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_SYNC) {
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mc->tms[0] = MC_TMS_SYNC_VALID;
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mc->tms[0] = MC_TMS_SYNC_VALID;
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}
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}
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while (mem_dev) {
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/* Grab control over all the devices we are destined to control */
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mem_dev->valid = 0;
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cur = mc_areas;
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mem_dev = mem_dev->next;
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prev = NULL;
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while (cur) {
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if (cur->mc == mc->index) {
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if (prev) prev->next = cur->next;
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else mc_areas = cur->next;
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prev = cur;
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tmp = cur->next;
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cur->next = mc->mc_areas;
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mc->mc_areas = cur;
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cur = tmp;
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} else {
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prev = cur;
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cur = cur->next;
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}
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}
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}
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for (cur = mc->mc_areas; cur; cur = cur->next)
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set_mem_valid(cur->mem, 0);
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set_csc_tms (0, mc->csc[0], mc->tms[0], mc);
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set_csc_tms (0, mc->csc[0], mc->tms[0], mc);
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}
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}
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void mc_status(void *dat)
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void mc_status(void *dat)
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| Line 194... |
Line 235... |
PRINTF( "CE %02d - CSC: 0x%08lX TMS: 0x%08lX\n", i, mc->csc[i],
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PRINTF( "CE %02d - CSC: 0x%08lX TMS: 0x%08lX\n", i, mc->csc[i],
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mc->tms[i]);
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mc->tms[i]);
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}
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}
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}
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}
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/*-----------------------------------------------------[ MC configuration }---*/
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/*--------------------------------------------[ Peripheral<->MC interface ]---*/
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/* Registers some memory to be under the memory controllers control */
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void mc_reg_mem_area(struct dev_memarea *mem, unsigned int cs, int mc)
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{
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struct mc_area *new;
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if(!(new = malloc(sizeof(struct mc_area)))) {
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fprintf(stderr, "Out-of-memory\n");
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exit(-1);
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}
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new->cs = cs;
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new->mem = mem;
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new->mc = mc;
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new->next = mc_areas;
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mc_areas = new;
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}
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/*-----------------------------------------------------[ MC configuration ]---*/
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void mc_enabled(union param_val val, void *dat)
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void mc_enabled(union param_val val, void *dat)
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{
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{
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struct mc *mc = dat;
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struct mc *mc = dat;
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mc->enabled = val.int_val;
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mc->enabled = val.int_val;
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}
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}
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| Line 213... |
Line 272... |
{
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{
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struct mc *mc = dat;
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struct mc *mc = dat;
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mc->poc = val.int_val;
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mc->poc = val.int_val;
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}
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}
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void mc_index(union param_val val, void *dat)
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{
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struct mc *mc = dat;
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mc->index = val.int_val;
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}
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void *mc_sec_start(void)
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void *mc_sec_start(void)
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{
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{
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struct mc *new = malloc(sizeof(struct mc));
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struct mc *new = malloc(sizeof(struct mc));
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if(!new) {
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if(!new) {
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fprintf(stderr, "Peripheral MC: Run out of memory\n");
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fprintf(stderr, "Peripheral MC: Run out of memory\n");
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exit(-1);
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exit(-1);
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}
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}
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new->index = 0;
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new->enabled = 0;
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new->enabled = 0;
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new->mc_areas = NULL;
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return new;
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return new;
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}
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}
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void mc_sec_end(void *dat)
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void mc_sec_end(void *dat)
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{
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{
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struct mc *mc = dat;
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struct mc *mc = dat;
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struct mem_ops ops;
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if(!mc->enabled) {
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if(!mc->enabled) {
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free(dat);
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free(dat);
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return;
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return;
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}
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}
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register_memoryarea(mc->baseaddr, MC_ADDR_SPACE, 4, 1, mc_read_word,
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/* FIXME: Check to see that the index given to this mc is unique */
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mc_write_word, dat);
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mc->next = mcs;
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mcs = mc;
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memset(&ops, 0, sizeof(struct mem_ops));
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ops.readfunc32 = mc_read_word;
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ops.writefunc32 = mc_write_word;
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ops.write_dat32 = dat;
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ops.read_dat32 = dat;
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/* FIXME: Correct delays? */
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ops.delayr = 2;
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ops.delayw = 2;
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reg_mem_area(mc->baseaddr, MC_ADDR_SPACE, 1, &ops);
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reg_sim_reset(mc_reset, dat);
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reg_sim_reset(mc_reset, dat);
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reg_sim_stat(mc_status, dat);
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reg_sim_stat(mc_status, dat);
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}
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}
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void reg_mc_sec(void)
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void reg_mc_sec(void)
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| Line 249... |
Line 332... |
struct config_section *sec = reg_config_sec("mc", mc_sec_start, mc_sec_end);
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struct config_section *sec = reg_config_sec("mc", mc_sec_start, mc_sec_end);
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reg_config_param(sec, "enabled", paramt_int, mc_enabled);
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reg_config_param(sec, "enabled", paramt_int, mc_enabled);
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reg_config_param(sec, "baseaddr", paramt_addr, mc_baseaddr);
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reg_config_param(sec, "baseaddr", paramt_addr, mc_baseaddr);
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reg_config_param(sec, "POC", paramt_int, mc_POC);
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reg_config_param(sec, "POC", paramt_int, mc_POC);
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reg_config_param(sec, "index", paramt_int, mc_index);
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}
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}
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No newline at end of file
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No newline at end of file
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